STA50813TR

STA508 Datasheet 40 V, 4.5 A quad power half bridge Features PowerSO-36 with exposed pad up • • • Multipower BCD technology Minimum input output pulse width distortion 200 mΩ RdsON complementary DMOS output stage • • • • CMOS compatible logic input Thermal protection Thermal warning output Undervoltage protection Description STA508 is a monolithic quad half bridge stage in Multipower BCD technology. The device can be used as dual bridge or reconfigured, by connecting CONFIG pin to Vdd pin, as single bridge with double current capability, and as half bridge (Binary mode) with half current capability. The device is particularly designed to make the output stage of a stereo all-digital high efficiency (DDX™) amplifier capable to deliver 80 + 80 W @ THD = 10 % at VCC = 35 V output power on 8 Ω load. In single BTL configuration is also capable to deliver a peak of 160 W @ THD = 10 % at VCC = 35 V on 4 Ω load. The input pins have threshold proportional to VL pin voltage. Maturity status link STA508 Device summary Order code STA50813TR Package PowerSO-36 (EPU) DS3503 - Rev 6 - November 2020 For further information contact your local STMicroelectronics sales office. www.st.com STA508 Diagram 1 Diagram Figure 1. Block diagram +VCC VCC1A IN1A VL 23 24 PWRDN PWRDN 25 R59 10K FAULT 27 C58 100nF TH_WAR IN1B C58 100nF C53 100nF C60 100nF 26 28 IN1B 30 VDD 21 VDD 22 VSS 33 VSS 34 M2 PROTECTIONS & LOGIC GND1A 12 VCC1B IN2A REGULATORS 13 GND1B 7 VCC2A IN2B GNDSUB 8 M15 31 20 M16 1 C32 1µF GND2A 4 VCC2B OUT2B OUT2B M14 5 8Ω C21 100nF C110 100nF C109 330pF R103 6 C33 1µF 3 R100 6 C99 100nF C23 470nF C101 100nF L113 22µH OUT2A 6 R98 6 L19 22µH OUT2A 2 32 R63 20 OUT1B OUT1B M4 9 19 C20 100nF C52 330pF C31 1µF 11 C55 1000µF L18 22µH OUT1A 14 10 35 36 C30 1µF OUT1A M17 VCCSIGN GND-Clean DS3503 - Rev 6 16 M5 TH_WAR GND-Reg IN2B 17 TRI-STATE VCCSIGN IN2A M3 29 CONFIG +3.3V R57 10K IN1A 15 R104 20 R102 6 C107 100nF C108 470nF C106 100nF 8Ω C111 100nF L112 22µH GND2B page 2/19 STA508 Pin configuration 2 Pin configuration Figure 2. Pin connection (top view) VCCSign 36 1 GND-SUB VCCSign 35 2 OUT2B VSS 34 3 OUT2B VSS 33 4 VCC2B IN2B 32 5 GND2B IN2A 31 6 GND2A IN1B 30 7 VCC2A IN1A 29 8 OUT2A TH_WAR 28 9 OUT2A FAULT 27 10 OUT1B TRI-STATE 26 11 OUT1B PWRDN 25 12 VCC1B CONFIG 24 13 GND1B VL 23 14 GND1A VDD 22 15 VCC1A VDD 21 16 OUT1A GND-Reg 20 17 OUT1A GND-Clean 19 18 N.C. Table 1. Pin description DS3503 - Rev 6 Pin N° Name 1 GND-SUB 2, 3 OUT2B Output half bridge 2B 4 VCC 2B Positive supply 5 GND2B Negative supply 6 GND2A Negative supply 7 VCC 2A Positive supply 8, 9 OUT2A Output half bridge 2A 10, 11 OUT1B Output half bridge 1B 12 VCC 1B Positive supply 13 GND1B Negative supply 14 GND1A Negative supply 15 VCC 1A Positive supply 16, 17 OUT1A Output half bridge 1A 18 NC Not connected 19 GND-clean Logical ground 20 GND-Reg Ground for regulator Vdd Description Substrate ground page 3/19 STA508 Pin configuration Pin N° Name Description 21, 22 Vdd 5 V Regulator referred to Ground 23 VL High logical state setting voltage 24 CONFIG Configuration pin 25 PWRDN Stand-by pin 26 TRI-STATE 27 FAULT 28 TH-WAR 29 IN1A Input of half bridge 1A 30 IN1B Input of half bridge 1B 31 IN2A Input of half bridge 2A 32 IN2B Input of half bridge 2B 33, 34 VSS 5 V regulator referred to + VCC 35, 36 VCC Sign Hi-Z pin Fault pin advisor Thermal warning advisor Signal positive supply Table 2. Functional pin status Pin name Logical value FAULT 0 Fault detected (Short circuit, or Thermal ..) FAULT (1) 1 Normal operation TRI-STATE 0 Allpowers in Hi-Z state TRI-STATE 1 Normal operation PWRDN 0 Low absorbion PWRDN 1 Normal operation THWAR 0 Temperature of the IC = 130 °C THWAR (1) 1 Normal operation CONFIG 0 Normal Operation CONFIG (2) 1 OUT1A = OUT1B; OUT2A=OUT2B (If IN1A = IN1B; IN2A = IN2B) IC-STATUS 1. The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor. 2. To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd). DS3503 - Rev 6 page 4/19 STA508 Maximum ratings 3 Maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit VCC DC supply voltage (Pin 4, 7, 12, 15) 40 V Vmax Maximum voltage on pins 23 to 32 5.5 V Ptot Power dissipation (Tcase = 70 °C) 50 W Top Operating temperature range - 40 to 90 °C Tstg Storage temperature Tj Junction temperature - 40 to 150 °C Value Unit max 1.5 °C/W Table 4. Thermal data Symbol Rthj-case DS3503 - Rev 6 Description Thermal resistance junction-case page 5/19 STA508 Electrical characteristics 4 Electrical characteristics Table 5. Electrical characteristics VL = 3.3 V; VCC = 30 V; Tamb = 25 °C ; fsw = 384 kHz unless otherwise specified. Symbol RdsON Parameter Power P-channel/N-channel MOSFET RdsON Test conditions Min. Id = 1 A Typ. Max. Unit 200 270 mΩ 50 µA Idss Power P-channel/N-channel leakage Idss VCC = 35 V gN Power P-channel RdsON matching Id = 1 A 95 % gP Power N-channel RdsON matching Id = 1 A 95 % Low current dead time (static) See Figure 5 Dt_s 10 20 ns 50 ns L = 22 µH; C = 470 nF; Dt_d High current dead time (dinamic) RL = 8 Ω Id = 3.5 A; see Figure 5 td ON Turn-on delay time Resistive load 100 ns td OFF Turn-off delay time Resistive load 100 ns tr Rise time Resistive load; as Figure 3 25 ns tf Fall time Resistive load; as Figure 3 25 ns 36 V VL/2 +300 mV V VCC Supply voltage operating voltage 10 VIN-High High level input voltage VIN-Low Low level input voltage IIN-High High level input current Pin voltage = VL 1 µA IIN-Low Low level input current Pin voltage = 0.3 V 1 µA 35 µA IPWRDN-H VL/2-300 mV High level PWRDN pin input current VL = 3.3 V VL Low logical state voltage VL (pin PWRDN, TRISTATE) (1) VL = 3.3 V VH High logical state voltage VH (pin PWRDN, TRISTATE) (1) VL = 3.3 V Supply CURRENT from VCC in Power Down PWRDN = 0 IFAULT Output current pins Fault -th-warn when Fault conditions Vpin = 3.3 V IVCC-hiz Supply current from VCC in Tri-state VCC = 30 V; Tri-state = 0 IVCC- PWRDN V 0.8 V 1.7 V 3 mA 1 mA 22 mA 50 mA VCC= 30 V; IVCC Supply current from VCC in operation both channel switching) Input pulse width = 50% duty; Switching frequency = 384 kHz; No LC filters IVCC-q VUV DS3503 - Rev 6 Isc (short circuit current limit) .(2) Undervoltage protection threshold 4.5 6 7 9 A V page 6/19 STA508 Electrical characteristics Symbol Parameter tpw-min Test conditions Output minimum pulse width Min. No load Typ. 70 Max. Unit 150 ns 1. See Table 6. VLow, VHigh variation with VL. 2. See relevant Application Note AN1994 Table 6. VLow, VHigh variation with VL VL VLow min VHigh max Unit 2.7 0.7 1.5 V 3.3 0.8 1.7 V 5 0.85 1.85 V Table 7. Logic truth table (see fig. 5) DS3503 - Rev 6 Tri-state INxA INxB Q1 Q2 Q3 Q4 Output mode 0 x x OFF OFF OFF OFF Hi-Z 1 0 0 OFF OFF ON ON DUMP 1 0 1 OFF ON ON OFF NEGATIVE 1 1 0 ON OFF OFF ON POSITIVE 1 1 1 ON ON OFF OFF Not used page 7/19 STA508 Test circuits and typical application diagrams 5 Test circuits and typical application diagrams Figure 3. Test circuit 1 OUTxY Vcc (3/4)Vcc Low current dead time = MAX (DTr, DTf) (1/2)Vcc (1/4)Vcc +Vcc t DTr Duty cycle = 50% DTf M58 OUTxY INxY R 8Ω M57 V67 = vdc = Vcc/2 + - gnd Figure 4. Test circuit 2 +VCC Q1 Q2 OUTxA INxA OUTxB Q3 INxB Q4 GND Figure 5. Test circuit 3 High Current Dead time for Bridge application = ABS [DTout(A) - DTin(A)] + ABS [DTOUT(B) - DTin(B)] +VCC Duty cycle = A Duty cycle = B DTout(A) M58 DTin(A) Q1 Q2 Rload = 8 Ω OUTA INA Iout = 4 A M57 Q3 DTout(B) L67 22 µ C69 470 nF L68 22 µ C71 470 nF C70 470 nF M64 DTin(B) OUTB INB Iout = 4 A Q4 M63 Duty cycle A and B: Fixed to have DC output current of 4 A in the direction shown in figure DS3503 - Rev 6 page 8/19 STA508 Test circuits and typical application diagrams Figure 6. Typical single BTL configuration VL +3.3V GND-Clean GND-Reg 100nF X7R 10K 23 18 N.C. 10µH 100nF VDD VDD CONFIG TH_WAR TH_WAR PWRDN nPWRDN FAULT 10K IN1A IN1B IN1A IN2A IN2B IN1B VSS VSS 100nF X7R 16 20 11 10 21 22 9 24 8 28 3 2 25 27 TRI-STATE 100nF 17 19 VCCSIGN 100nF X7R VCCSIGN Add. GNDSUB 15 26 29 12 30 31 7 OUT1A 100nF FILM OUT1A 22Ω 1/2W OUT1B OUT1B OUT2A OUT2A 330pF 4 34 14 35 13 36 6 1 5 6.2 1/2W OUT2B 100nF X7R 470nF FILM 100nF X7R 4Ω 100nF FILM OUT2B 10µH VCC1A 32V 1µF X7R VCC1B 2200µF 63V VCC2A 32V 1µF X7R 32 33 6.2 1/2W VCC2B GND1A GND1B GND2A GND2B Figure 7. Typical quad half bridge configuration +VCC VCC1P IN1A +3.3V PWRDN R57 10K R59 10K C58 100nF TH_WAR IN1B C58 100nF C53 100nF C60 100nF IN1A VL 23 CONFIG 24 PWRDN 25 FAULT 26 28 IN1B 30 VDD 21 VDD 22 VSS 33 VSS 34 15 16 M2 PROTECTIONS & LOGIC OUTPL OUTPL 14 PGND1P 12 VCC1N C51 1µF 11 10 REGULATORS 13 7 R41 20 C41 330pF PGND1N VCC2P C71 100nF R51 6 C81 100nF C61 100nF OUTNL OUTNL M4 R61 5K L11 22µH 17 M5 TH_WAR R42 20 C42 330pF VCCSIGN C72 100nF R52 6 C82 100nF IN2A GND-Reg IN2B GNDSUB 9 36 M15 31 20 19 M16 1 OUTPR 6 PGND2P 4 VCC2N C52 1µF 3 2 32 OUTPR 5 C43 330pF PGND2N C73 100nF R53 6 C83 100nF C62 100nF OUTNR OUTNR M14 R43 20 C44 330pF R66 5K R67 5K L14 22µH R44 20 R64 5K R65 5K L13 22µH 8 35 R62 5K R63 5K L12 22µH M17 GND-Clean IN2B 27 M3 TRI-STATE VCCSIGN IN2A 29 C74 100nF R54 6 C84 100nF R68 5K C21 2200µF C31 820µF C91 1µF 4Ω C32 820µF C92 1µF 4Ω C33 820µF C93 1µF 4Ω C34 820µF C94 1µF 4Ω For more information refer to the application note AN1661. DS3503 - Rev 6 page 9/19 STA508 Package information 6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DS3503 - Rev 6 page 10/19 STA508 PowerSO-36 exposed pad up package information 6.1 PowerSO-36 exposed pad up package information Figure 8. PowerSO-36 exposed pad up package outline BOTTOM VIEW TOP VIEW DS3503 - Rev 6 page 11/19 STA508 PowerSO-36 exposed pad up package information Figure 9. PowerSO-36 section A-A and B-B package outline SECTION A-A NOT TO SCALE SECTION B-B NOT TO SCALE DS3503 - Rev 6 page 12/19 STA508 PowerSO-36 exposed pad up package information Table 8. PowerSO-36 package mechanical data Dim. mm Min. Typ. Max. Ɵ 0° - 8° Ɵ1 5° - 10° Ɵ2 0° - - A - - 3.41 A1 0.30 - -0.40 A2 3.10 3.14 3.18 A3 - 0.2 - A4 0.80 - 1.00 b 0.22 - 0.41 b1 0.22 - 0.38 c 0.23 - 0.32 c1 0.23 0.25 0.29 D 15.90 BSC D1 VARIATION D2 D3 DS3503 - Rev 6 - - 1.00 5.00 - e 0.65 BSC E 14.20 BSC E1 11.00 BSC E2 VARIATION E3 - - 2.90 h - - 1.10 L 0.80 - 1.10 L1 1.60 REF L2 0.35 BSC N 36 R 0.20 - - R1 0.20 - - s 0.25 - - page 13/19 STA508 PowerSO-36 exposed pad up package information Table 9. Tolerance of form and position Symbol Databook aaa 0.10 bbb 0.30 ccc 0.075 ddd 0.25 eee 0.10 ggg 0.25 Note 1.2 Table 10. Variations Symbol DS3503 - Rev 6 Databook Min. Typ. Max. D1 9.40 - 9.80 E2 5.80 - 6.20 Opt. A page 14/19 STA508 Revision history Table 11. Document revision history DS3503 - Rev 6 Date Revision Changes Sep 1994 1 Initial release. Jun 2004 2 Note 2: See relevant Application Note AN1994 Nov 2004 3 Changed VCC from 9 min to 10 min Feb 2006 4 Changed Top value on Table 5. 01-Sep-2020 5 Updated order code in device summary on the cover page. 19-Nov-2020 6 Updated package name, Figure 2 and Section 6.1 PowerSO-36 exposed pad up package information. page 15/19 STA508 Contents Contents 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 4 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Test circuits and typical application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 6.1 PowerSO36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 DS3503 - Rev 6 page 16/19 STA508 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical characteristics VL = 3.3 V; VCC = 30 V; Tamb = 25 °C ; fsw = 384 kHz unless otherwise specified. VLow, VHigh variation with VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic truth table (see fig. 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSO-36 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tolerance of form and position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3503 - Rev 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 4 . 5 . 5 . 6 . 7 . 7 13 14 14 15 page 17/19 STA508 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. DS3503 - Rev 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . Pin connection (top view) . . . . . . . . . . . . . . . . . . Test circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . Test circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . Test circuit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical single BTL configuration . . . . . . . . . . . . . Typical quad half bridge configuration . . . . . . . . . PowerSO-36 exposed pad up package outline . . . PowerSO-36 section A-A and B-B package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 3 . 8 . 8 . 8 . 9 . 9 11 12 page 18/19 STA508 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2020 STMicroelectronics – All rights reserved DS3503 - Rev 6 page 19/19