STA510A
44 V, 5.5 A, quad power half-bridge
Datasheet - production data
Description
The STA510A is a monolithic, quad, half-bridge
stage in multipower BCD technology. The device
can be used as dual-bridge or reconfigured, by
connecting the CONFIG pin to the VDD pin, as
single-bridge with double current capability, or as
half-bridge (binary mode) with half current
capability.
• Minimum input/output pulse width distortion
The device is particularly designed to make the
output stage of a stereo all-digital high-efficiency
(DDX) amplifier, which employs a pulse-width
modulator driver. The STA510A is capable of
delivering an output power of 50 W into 3 Ω loads
with THD = 10% and VCC = 36 V. In single BTL
configuration the device can deliver 200 W into a
3 Ω load with THD = 10% and VCC = 36 V.
• 150 mΩ RDS(on) complementary DMOS output
stage
The input pins have a threshold proportional to VL
pin voltage.
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Features
• Multipower BCD technology
• CMOS compatible logic inputs
• Thermal protection
• Thermal warning output
• Undervoltage protection
• Short-circuit protection
Table 1. Device summary
Order code
Operating temp. range
Package
Packing
STA510A13TR
0 ° to 70 °C
PowerSO-36 (slug up)
Tape and reel
October 2020
This is information on a product in full production.
DocID11077 Rev 4
1/21
www.st.com
Contents
STA510A
Contents
1
Audio application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
5
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.4
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Technical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
Logic interface and decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.2
Protection circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3
Power outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4
Parallel output / high current operation . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5
Output filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.6
Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1
6
2/21
PowerSO-36 exposed pad up package information . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DocID11077 Rev 4
STA510A
1
Audio application circuit
Audio application circuit
Figure 1. TAudio application circuit (dual BTL)
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Pin description
2
STA510A
Pin description
Figure 2. Pin connections (top view)
VCCSign
36
1
GND-SUB
VCCSign
35
2
OUT2B
VSS
34
3
OUT2B
VSS
33
4
VCC2B
IN2B
32
5
GND2B
IN2A
31
6
GND2A
IN1B
30
7
VCC2A
IN1A
29
8
OUT2A
TH_WAR
28
9
OUT2A
FAULT
27
10
OUT1B
TRI-STATE
26
11
OUT1B
PWRDN
25
12
VCC1B
CONFIG
24
13
GND1B
VL
23
14
GND1A
VDD
22
15
VCC1A
VDD
21
16
OUT1A
GND-Reg
20
17
OUT1A
GND-Clean
19
18
N.C.
Table 2. Pin list
4/21
Pin
Name
Description
1
GND-SUB
2, 3
OUT2B
Output half-bridge 2B
4
Vcc2B
Positive supply
5
GND2B
Negative supply
6
GND2A
Negative supply
7
Vcc2A
Positive supply
8, 9
OUT2A
Output half-bridge 2A
10, 11
OUT1B
Output half-bridge 1B
12
Vcc1B
Positive supply
13
GND1B
Negative supply
14
GND1A
Negative supply
15
Vcc1A
Positive supply
16, 17
OUT1A
Output half-bridge 1A
18
NC
Substrate ground
Not connected
DocID11077 Rev 4
STA510A
Pin description
Table 2. Pin list (continued)
Pin
Name
Description
19
GND-clean
Logical ground
20
GND-Reg
Ground for regulator VDD
21, 22
VDD
5-V regulator referred to ground
23
VL
High logical state setting voltage
CONFIG
Configuration
0: normal operation
1: single BTL (mono) mode, join the pins OUT1A to OUT1B and
OUT2A to OUT2B (if IN1A is joined to IN1B and IN2A to IN2B)
25
PWRDN
Standby (power down):
0: low power consumption mode
1: normal operation
26
TRI-STATE
27
FAULT(1)
Fault advisor:
0: fault detected (short circuit or thermal)
1: normal operation
28
TH-WAR
Thermal warning advisor:
0: junction temperature = 130 °C
1: normal operation
29
IN1A
Input of half-bridge 1A
30
IN1B
Input of half-bridge 1B
31
IN2A
Input of half-bridge 2A
32
IN2B
Input of half-bridge 2B
33, 34
VSS
5-V regulator referred to +VCC
35, 36
VCCSIGN
-
EP
24
High impedance control:
0: all power amplifiers in high-impedance state
1: normal operation
Signal positive supply
Exposed pad up
1. The pin is open collector. To have a high logic value it needs to be pulled up by a resistor.
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Electrical specifications
STA510A
3
Electrical specifications
3.1
Absolute maximum ratings
Table 3. Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
DC supply voltage (pin 4, 7, 12, 15)
44
V
Vmax
Maximum voltage on pins 23 to 32
5.5
V
Ptot
Power dissipation (Tcase = 70 °C)
21
W
Top
Operating temperature range
90
°C
-40 to 150
°C
Tstg, Tj
3.2
Storage and junction temperature
Recommended operating conditions
Table 4. Recommended operating conditions(1)
Symbol
Parameter
Min.
Vcc
DC supply voltage
10
VL
Input logic reference
2.7
Tamb
Ambient temperature
0
Typ.
3.3
Max.
Unit
39.0
V
5.0
V
70
°C
1. Performance not guaranteed beyond recommended operating conditions.
3.3
Thermal data
The power dissipated within the device depends primarily on the supply voltage, load
impedance and output modulation level. The PowerSO36 package of the STA510A includes
an exposed pad or slug on the top of the device to provide a direct thermal path from the die
to the heatsink.
Table 5. Thermal data
Symbol
Tj-case
Parameter
Thermal resistance junction to case (thermal pad)
Min.
Typ.
Max.
Unit
1
2.5
°C/W
TjSD
Thermal shut-down junction temperature
150
°C
Twarn
Thermal warning temperature
130
°C
thSD
Thermal shutdown hysteresis
25
°C
6/21
DocID11077 Rev 4
STA510A
3.4
Electrical specifications
Electrical specifications
The results in Table 6 below are given for the conditions: VL = 3.3 V, VCC = 36 V, RL = 8 Ω,
fsw= 384 kHz and Tamb = 25 °C unless otherwise specified. See also Figure 3.
Table 6. Electrical specifications
Symbol
RdsON
Parameter
Conditions
Power P-channel/N-channel
MOSFET RDS(on)
Min.
Id = 1 A
Typ.
Max.
Unit
150
200
mΩ
100
μA
Idss
Power P-channel/N-channel leakage
current
gN
Power P-channel RDS(on) matching
Id = 1 A
95
%
gP
Power N-channel RDS(on) matching
Id = 1 A
95
%
Dt_s
Low current deadtime (static)
See test circuit Figure 3
Dt_d
High current deadtime (dynamic)
td ON
td OFF
10
20
ns
L = 22 µH, C = 470 nF,
RL = 8 Ω, Id = 3 A,
see test circuit Figure 5
50
ns
Turn-on delay time
Resistive load, VCC = 30 V
100
ns
Turn-off delay time
Resistive load, VCC = 30 V
100
ns
tr
Rise time
Resistive load, as Figure 3
25
ns
tf
Fall time
Resistive load, as Figure 3
25
ns
VL/2 +
300 mV
V
VIN-High
High level input voltage
VIN-Low
Low level input voltage
IIN-H
High level input current
Pin voltage = VL
1
μA
IIN-L
Low level input current
Pin voltage = 0.3 V
1
μA
VL= 3.3 V
35
μA
VL/2 –
300 mV
IPWRDN-H High level PWRDN pin input current
VLow
VHigh
IVCC-
Low logical state voltage (pins
PWRDN, TRISTATE)
High logical state voltage (pins
PWRDN, TRISTATE)
V
VL = 2.7 V
0.70
VL= 3.3 V
0.80
VL= 5.0 V
0.85
V
VL = 2.7 V
1.50
V
VL = 3.3 V
1.7
V
VL= 5.0 V
1.85
V
Supply current from VCC in power
down
PWRDN = 0
IFAULT
Output current pins FAULT -THWARN when FAULT CONDITIONS
VPIN = 3.3 V
1
mA
IVCC-hiz
Supply current from VCC in tri-state
VCC = 30 V, Pin TRI-STATE
=0
22
mA
PWRDN
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mA
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21
Electrical specifications
STA510A
Table 6. Electrical specifications (continued)
Symbol
Parameter
Conditions
IVCC
VCC = 30 V, input pulse width
Supply current from VCC in operation duty cycle = 50%, switching
frequency = 384 kHz, no LC
both channel switching)
filters;
ISCP
Short-circuit current limit
VUV
Undervoltage protection threshold
tpw_min
ESD
8/21
Min.
5.5
Output minimum pulse width
No load
ESD maximum withstanding voltage
range, test condition CDF-AECQ100-002-”Human Body Model”
DocID11077 Rev 4
Typ.
Max.
Unit
70
mA
6
A
7
V
25
40
± 1500
ns
V
STA510A
Electrical specifications
Table 7. Logic truth table
TRI-STATE
INxA
INxB
Q1
Q2
Q3
Q4
Output mode
0
x
x
OFF
OFF
OFF
OFF
Hi-Z
1
0
0
OFF
OFF
ON
ON
DUMP
1
0
1
OFF
ON
ON
OFF
NEGATIVE
1
1
0
ON
OFF
OFF
ON
POSITIVE
1
1
1
ON
ON
OFF
OFF
Not used
Figure 3. Test circuit for low current deadtime for single-ended applications
OUTxY
Vcc
(3/4)Vcc
Low current dead time = MAX(DTr,DTf)
(1/2)Vcc
(1/4)Vcc
+Vcc
t
DTr
Duty cycle = 50%
DTf
M58
OUTxY
INxY
R 8Ω
M57
+
-
V67 =
vdc = Vcc/2
gnd
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Figure 4. Test circuit for high current deadtime for bridge applications
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+VCC
Duty cycle=A
Duty cycle=B
DTout(A)
M58
DTin(A)
Q1
Q2
OUTxA
INxA
Iout=4.5A
M57
Q3
DTout(B)
Rload=8Ω
L67 22μ
C69
470nF
L68 22μ
C71 470nF
C70
470nF
DTin(B)
OUTxB
INxB
Iout=4.5A
Q4
Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure
DocID11077 Rev 4
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21
Electrical specifications
STA510A
Figure 5. Block diagram for high current dead time for bridge applications
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STA510A
4
Technical information
Technical information
The STA510A is a dual channel H-bridge that is able to deliver 100 W per channel (into RL =
6 Ω with THD = 10% and VCC = 36 V) of audio output power very efficiently. It operates in
conjunction with a pulse-width modulator driver such as the STA321 or STA309A.
The STA510A converts ternary-, phase-shift- or binary-controlled PWM signals into audio
power at the load. It includes a logic interface, integrated bridge drivers, high efficiency
MOSFET outputs and thermal and short-circuit protection circuitry. In differential mode
(ternary, phase-shift or binary differential), two logic level signals per channel are used to
control high-speed MOSFET switches to connect the speaker load to the input supply or to
ground in a bridge configuration, according to the damped ternary modulation operation.
In binary mode, both full bridge and half bridge modes are supported. The STA510A
includes overcurrent and thermal protection as well as an undervoltage lockout with
automatic recovery. A thermal warning status is also provided.
Figure 6. Block diagram of full-bridge DDX® or binary mode
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4.1
Logic interface and decode
The STA510A power outputs are controlled using one or two logic-level timing signals. In
order to provide a proper logic interface, the VL input must operate at the same voltage as
the DDX control logic supply.
DocID11077 Rev 4
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21
Technical information
4.2
STA510A
Protection circuitry
The STA510A includes protection circuitry for overcurrent and thermal overload conditions.
A thermal warning pin (THWARN, pin 28, open drain MOSFET) is activated low when the IC
temperature exceeds 130 °C, just in advance of thermal shutdown. When a fault condition is
detected an internal fault signal immediately disables the output power MOSFETs, placing
both H-bridges in a high-impedance state. At the same time the open-drain MOSFET of pin
FAULT (pin 27) is switched on.
There are two possible modes subsequent to activating a fault.
4.3
•
Shutdown mode: with pins FAULT (with pull-up resistor) and TRISTATE separate, an
activated fault disables the device, signalling a low at pin FAULT output. The device
may subsequently be reset to normal operation by toggling pin TRISTATE from high to
low to high using an external logic signal.
•
Automatic recovery mode: This is shown in the applications circuits below where pins
FAULT and TRISTATE are connected together to a time-constant circuit (R59 and
C58). An activated fault forces a reset on pin TRISTATE causing normal operation to
resume following a delay determined by the time constant of the circuit. If the fault
condition persists, the circuit operation repeats until the fault condition is cleared. An
increase in the time constant of the circuit produces a longer recovery interval. Care
must be taken in the overall system design not to exceed the protection thesholds
under normal operation.
Power outputs
The STA510A power and output pins are duplicated to provide a low-impedance path for the
device bridged outputs. All duplicate power, ground and output pins must be connected for
proper operation.
The PWRDN or TRISTATE pin should be used to set all power MOSFETs to the highimpedance state during power-up until the logic power supply, VL, has settled.
4.4
Parallel output / high current operation
When using the DDX mode output, the STA510A outputs can be connected in parallel in
order to increase the output current capability to a load. In this configuration the STA510A
can provide up to 200 W into a 3-Ω load.
This mode of operation is enabled with the pin CONFIG (pin 24) connected to pin VDD. The
inputs are joined so that IN1A = IN1B, IN2A = IN2B and similarly the outputs OUT1A =
OUT1B, OUT2A = OUT2B as shown in Figure 9.
4.5
Output filtering
A passive 2nd-order filter is used on the STA510A power outputs to reconstruct the analog
audio signal. System performance can be significantly affected by the output filter design
and choice of passive components. A filter design for 6- or 8-Ω loads is shown in the
application circuit of Figure 8, and for 4-Ω loads in Figure 9 and Figure 10.
12/21
DocID11077 Rev 4
STA510A
4.6
Technical information
Application circuits
Figure 8. Typical stereo full bridge configuration for up to 2x 100 W
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Figure 9. Typical single BTL configuration for up to 180 W
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Technical information
STA510A
Figure 10. Typical quad half-bridge configuration for up to 4x 50 W
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In the above three circuits a PWM modulator as driver is needed.
The power estimations were made using the STA321+STA510A demo board. The peak
power duration is for t ≤1 s.
14/21
DocID11077 Rev 4
STA510A
5
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
DocID11077 Rev 4
15/21
21
Package information
5.1
STA510A
PowerSO-36 exposed pad up package information
Figure 11. PowerSO-36 exposed pad up package outline
16/21
DocID11077 Rev 4
STA510A
Package information
Figure 12. PowerSO-36 section A-A and B-B package outline
DocID11077 Rev 4
17/21
21
Package information
STA510A
Table 8. PowerSO-36 package mechanical data
mm
Dim.
Min.
Typ.
Max.
Ɵ
0°
-
8°
Ɵ1
5°
-
10°
Ɵ2
0°
-
-
A
-
-
3.41
A1
0.30
-
-0.40
A2
3.10
3.14
3.18
A3
-
0.2
-
A4
0.80
-
1.00
b
0.22
-
0.41
b1
0.22
-
0.38
c
0.23
-
0.32
c1
0.23
0.25
0.29
D
15.90 BSC
D1
VARIATION
D2
-
1.00
5.00
-
D3
18/21
-
e
0.65 BSC
E
14.20 BSC
E1
11.00 BSC
E2
VARIATION
E3
-
-
2.90
h
-
-
1.10
L
0.80
-
1.10
L1
1.60 REF
L2
0.35 BSC
N
36
R
0.20
-
-
R1
0.20
-
-
s
0.25
-
-
DocID11077 Rev 4
STA510A
Package information
Table 9. Tolerance of form and position
Symbol
Databook
aaa
0.10
bbb
0.30
ccc
0.075
ddd
0.25
eee
0.10
ggg
0.25
Note
1.2
Table 10. Variations
Databook
Symbol
Opt.
Min.
Typ.
Max.
D1
9.40
-
9.80
E2
5.80
-
6.20
A
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Revision history
6
STA510A
Revision history
Table 11. Document revision history
20/21
Date
Revision
Changes
13-Oct-2004
1
Initial release.
11-Mar-2010
2
Updated description and applications circuits
15-Jan-2019
3
Removed the order code STA510A from the device summary table in
cover page.
22-Oct2020
4
Updated cover image and package information.
DocID11077 Rev 4
STA510A
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