STA510F
44 V, 5.5 A, quad power half-bridge
Datasheet - production data
Description
The STA510F is a monolithic, quad, half-bridge
stage in multipower BCD technology. The device
can be used as dual-bridge or reconfigured, by
connecting the CONFIG pin to the Vdd pin, as
single-bridge with double current capability, and
as half-bridge (binary mode).
The device is particularly designed to make the
output stage of a stereo all-digital high-efficiency
(FFX) amplifier capable of delivering 100 W +
100 W output power into 6 Ω loads with
THD = 10% and VCC = 36 V. In single BTL
configuration the device can deliver 200 W into a
3 Ω load with THD = 10% and VCC = 36 V.
PSSO36 (slug up)
Features
• Minimum input/output pulse width distortion
The device is fully compatible with the FFX®
driver device.
• 150 mΩ RDS(on) complementary DMOS output
stage
The input pins have a threshold proportional to VL
pin voltage.
• CMOS compatible logic inputs
• Thermal protection
• Thermal warning output
• Undervoltage protection
• No power-on, power-off sequence required
Table 1. Device summary
Order code
Operating temp. range
Package
Packing
STA510FTR
0° to 70° C
PSSO36 (slug up)
Tape and reel
December 2018
This is information on a product in full production.
DocID014268 Rev 5
1/26
www.st.com
Contents
STA510F
Contents
1
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5
Output filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1
Theoretical filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2
Optimized filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7
Trademarks and other acknowledgments . . . . . . . . . . . . . . . . . . . . . . . 24
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/26
DocID014268 Rev 5
STA510F
Application diagram
Figure 1. Typical application
Output Filter
PWM Out1_A
IN 1A
PWM Out2_A
IN 2A
STA311B
IN 1B
PWM Out2_B
IN 2B
PSU
OUT 1A
IN A
OUT 1B
IN B
OUT A
OUT B
SPEAKER
STA510F
PWM Out1_B
Vcc
1
Application diagram
Output Filter
OUT 2A
IN A
OUT 2B
IN B
OUT A
OUT B
SPEAKER
Vcc
GND
DocID014268 Rev 5
3/26
26
Pin description
2
STA510F
Pin description
Figure 2. Pin connections (top view)
VCCSign
36
1
GND-SUB
VCCSign
35
2
OUT2B
VSS
34
3
OUT2B
VSS
33
4
VCC2B
IN2B
32
5
GND2B
IN2A
31
6
GND2A
IN1B
30
7
VCC2A
IN1A
29
8
OUT2A
TH_WAR
28
9
OUT2A
FAULT
27
10
OUT1B
TRI-STATE
26
11
OUT1B
PWRDN
25
12
VCC1B
CONFIG
24
13
GND1B
VL
23
14
GND1A
VDD
22
15
VCC1A
VDD
21
16
OUT1A
GND-Reg
20
17
OUT1A
GND-Clean
19
18
N.C.
Table 2. Pin list
4/26
Pin
Name
Description
1
GND-SUB
2, 3
OUT2B
Output half-bridge 2B
4
Vcc2B
Positive supply
5
GND2B
Negative supply
6
GND2A
Negative supply
7
Vcc2A
Positive supply
8, 9
OUT2A
Output half-bridge 2A
10, 11
OUT1B
Output half-bridge 1B
12
Vcc1B
Positive supply
13
GND1B
Negative supply
14
GND1A
Negative supply
15
Vcc1A
Positive supply
16, 17
OUT1A
Output half-bridge 1A
18
NC
Substrate ground
Not connected
DocID014268 Rev 5
STA510F
Pin description
Table 2. Pin list (continued)
Pin
Name
Description
19
GND-clean
Logical ground
20
GND-Reg
Ground for regulator Vdd
21, 22
VDD
5-V regulator referred to ground
23
VL
High logical state setting voltage
24
CONFIG
Configuration
25
PWRDN
Standby
26
TRI-STATE
27
FAULT
28
TH-WAR
29
IN1A
Input of half-bridge 1A
30
IN1B
Input of half-bridge 1B
31
IN2A
Input of half-bridge 2A
32
IN2B
Input of half-bridge 2B
33, 34
Vss
5-V regulator referred to +VCC
35, 36
VCCSIGN
Hi-Z
Fault pin advisor
Thermal warning advisor
Signal positive supply
Table 3. Pin values
Pin
FAULT (1)
Logical value
Device status
0
Fault detected (short-circuit, or thermal)
1
Normal operation
0
All power stages in Hi-Z state
1
Normal operation
0
Low-power mode
1
Normal operation
0
Temperature of the IC = 130 °C
1
Normal operation
0
Normal operation
1
OUT1A = OUT1B, OUT2A = OUT2B
(IF IN1A = IN1B and IN2A = IN2B)
TRI-STATE
PWRDN
THWAR (1)
CONFIG (2)
1. The pin is open collector. To have the high logic value, it needs a pull-up resistor.
2. CONFIG = 1 means connect pin 24 (CONFIG) to pins 21, 22 (VDD).
DocID014268 Rev 5
5/26
26
Electrical specifications
STA510F
3
Electrical specifications
3.1
Absolute maximum ratings
Table 4. Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
DC supply voltage (pin 4, 7, 12, 15)
44
V
Vmax
Maximum voltage on pins 23 to 32
5.5
V
ESD
Max ESD on pins (HBM)
±1000
V
Operating temperature range
0 to 70
°C
-40 to 150
°C
Top
Tstg, Tj
3.2
Storage and junction temperature
Thermal data
Table 5. Thermal data
Symbol
Tj-case
Parameter
Min.
Thermal resistance junction to case (thermal pad)
Typ.
Max.
Unit
1
2.5
°C/W
TjSD
Thermal shut-down junction temperature
150
°C
Twarn
Thermal warning temperature
130
°C
thSD
Thermal shutdown hysteresis
25
°C
3.3
Electrical specifications
The results in Table 6 below are given for the conditions: VL = 3.3 V, VCC = 37 V and
T = 25 °C unless otherwise specified.
Table 6. Electrical specifications
Symbol
RdsON
Parameter
Conditions
Power P-channel/N-channel
MOSFET RDS(on)
Min.
Id = 1 A
Typ.
Max.
Unit
150
200
mΩ
100
μA
Idss
Power P-channel/N-channel leakage
current
gN
Power P-channel RDS(on) matching
Id = 1 A
95
%
gP
Power N-channel RDS(on) matching
Id = 1 A
95
%
Dt_s
Low current deadtime (static)
See test circuit Figure 3
Dt_d
High current deadtime (dynamic)
td ON
Turn-on delay time
6/26
20
ns
L = 22 µH, C = 470 nF,
RL = 8 Ω, Id = 4.5 A,
see test circuit Figure 4
50
ns
Resistive load
100
ns
DocID014268 Rev 5
10
STA510F
Electrical specifications
Table 6. Electrical specifications (continued)
Symbol
td OFF
Parameter
Conditions
Min.
Typ.
Max.
Unit
Turn-off delay time
Resistive load
100
ns
tr
Rise time
Resistive load, as Figure 4
25
ns
tf
Fall time
Resistive load, as Figure 4
25
ns
40
V
VCC
Supply voltage operating voltage
10
VL/2 +
300 mV
VIN-High
High level input voltage
VIN-Low
Low level input voltage
IIN-H
High level input current
Pin voltage = VL
1
μA
IIN-L
Low level input current
Pin voltage = 0.3 V
1
μA
VL= 3.3 V
35
μA
V
VL/2 –
300 mV
IPWRDN-H High level PWRDN pin input current
V
VLow
Low logical state voltage (pins
PWRDN, TRISTATE) (see Table 7)
VL = 3.3 V
VHigh
High logical state voltage (pins
PWRDN, TRISTATE) (see Table 7)
VL = 3.3 V
Supply current from VCC in power
down
PWRDN = 0
IFAULT
Output current pins FAULT -THWARN when FAULT CONDITIONS
VPIN = 3.3 V
1
mA
IVCC-hiz
Supply current from VCC in tri-state
Pin TRI-STATE = 0
22
mA
70
mA
IVCCPWRDN
IVCC
IOUT-SH
VUV
tpw_min
0.8
1.7
Overcurrent protection threshold ISC
(short-circuit current limit)
5.5
Undervoltage protection threshold
Output minimum pulse width
V
3
Input pulse width duty
Supply current from VCC in operation cycle = 50%, switching
frequency = 384 kHz, no LC
both channel switching)
filters;
7
9
7
No load
DocID014268 Rev 5
25
V
mA
A
V
40
ns
7/26
26
Electrical specifications
STA510F
Table 7. Vlow, Vhigh threshold variation with VL
VL
VLow max.
VHigh min.
Unit
2.7
0.7
1.5
V
3.3
0.8
1.7
V
5
0.85
1.85
V
Table 8. Logic truth table
TRI-STATE
INxA
INxB
Q1
Q2
Q3
Q4
Output mode
0
x
x
OFF
OFF
OFF
OFF
Hi-Z
1
0
0
OFF
OFF
ON
ON
DUMP
1
0
1
OFF
ON
ON
OFF
NEGATIVE
1
1
0
ON
OFF
OFF
ON
POSITIVE
1
1
1
ON
ON
OFF
OFF
Not used
Figure 3. Test circuit for low current deadtime
OUTxY
Vcc
(3/4)Vcc
Low current dead time = MAX(DTr,DTf)
(1/2)Vcc
(1/4)Vcc
+Vcc
t
DTr
Duty cycle = 50%
DTf
M58
OUTxY
INxY
R 8Ω
M57
+
-
V67 =
vdc = Vcc/2
gnd
D03AU1458
Figure 4. Test circuit for high current deadtime
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+VCC
Duty cycle=A
Duty cycle=B
DTout(A)
M58
DTin(A)
Q1
Q2
Rload=8Ω
OUTxA
INxA
Iout=4.5A
M57
Q3
DTout(B)
L67 22μ
C69
470nF
L68 22μ
C71 470nF
C70
470nF
DocID014268 Rev 5
DTin(B)
OUTxB
INxB
Iout=4.5A
Q4
Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure
8/26
M64
M63
D00AU1162
STA510F
Electrical specifications
Figure 5. STA311B connections with STA510F
DocID014268 Rev 5
9/26
26
Electrical specifications
STA510F
Figure 6. Typical stereo BTL configuration
Figure 7. Typical mono BTL configuration
10/26
DocID014268 Rev 5
STA510F
Electrical specifications
Figure 8. Typical quad half-bridge configuration
DocID014268 Rev 5
11/26
26
Characterization curves
4
STA510F
Characterization curves
Figure 9. THD+N vs. POUT 36 V 6 Ω BTL time slot 13, 0x03 = BB
*$06 6*
P P
P P P P
:
Figure 10. THD+N vs. POUT 36 V 3 Ω SE
*$06 6*
P
P
P P P
P
:
12/26
DocID014268 Rev 5
STA510F
Characterization curves
Figure 11. THD+N vs. POUT 36V 3 Ω mono BTL
*$066*
P P
P P P P
:
Figure 12. POUT vs. VCC 6 Ω BTL
*$066*
7+'
7+'
DocID014268 Rev 5
13/26
26
Characterization curves
STA510F
Figure 13. POUT vs. VCC 3 Ω SE
*$066*
7+'
7+'
Figure 14. POUT vs. VCC 3 Ω mono BTL
*$066*
7+'
7+'
14/26
DocID014268 Rev 5
STA510F
Characterization curves
Figure 15. FFT 6 Ω BTL -6dBFs
*$066*
G
%
U
$
N
N
N
N
N
+]
Figure 16. FFT 6 Ω BTL -60dBFs
*$066*
G
%
U
$
+]
DocID014268 Rev 5
N
N
N
N
N
15/26
26
Characterization curves
STA510F
Figure 17. FFT 3 Ω SE -6dBFs
*$066*
G
%
U
$
+]
N
N
N
N
N
Figure 18. FFT 3 Ω SE -60dBFs
*$066*
G
%
U
$
16/26
+]
DocID014268 Rev 5
N
N
N
N
N
STA510F
Characterization curves
Figure 19. FFT 3 Ω mono BTL -6dBFs
*$066*
G
%
U
$
+]
N
N
N
N
N
Figure 20. FFT 3 Ω mono BTL -60dBFs
*$066*
G
%
U
$
+]
DocID014268 Rev 5
N
N
N
N
N
17/26
26
Characterization curves
STA510F
Figure 21. Crosstalk 36 V 6 BTL Ω 1 W
*$066*
G
%
N
N
N
N
N
+]
Figure 22. Crosstalk 36 V 3 Ω SE 1 W
*$066*
G
%
+]
18/26
DocID014268 Rev 5
N
N
N
N
N
STA510F
5
Output filter
Output filter
The differential-mode damping of a hybrid filter under no-load conditions is not as good as a
pure common-mode filter because most of the high-frequency current flows through the
larger capacitor across the speaker terminals. Normally this isn't a problem because the
speaker provides the differential-mode damping, but if the amplifier is operated without the
speaker connected, for instance when doing testing in production line, then the damping will
not be as good.
Care needs to be taken to insure that the damping of a hybrid filter is good enough to protect
the amplifier under no-load conditions, thus avoiding peak of voltage that exceed the
absolute maximum voltage of the amplifier.
Figure 23. Output filter frequency response with and without load connected to the
amplifier
To allow the right filter selection both sets of coefficients are provided.
5.1
Theoretical filter
Perfect when using amplifiers always connected to speakers
Table 9. Theoretical table SE
Load
impedance
LC Low-pass filter
Damping network
LF
CF
CS
CP
RP
3
15 µH
1 µF
100 nF
100 nF
6.2 Ω
4
22 µH
680 nF
100 nF
100 nF
6.2 Ω
6
33 µH
470 nF
100 nF
100 nF
6.2 Ω
8
47 µH
330 nF
100 nF
100 nF
6.2 Ω
See Figure 8.
DocID014268 Rev 5
19/26
26
Output filter
STA510F
Table 10. Theoretical table BTL
Load
Impedance
LC Low-Pass Filter
Damping network
LF
CF
CS
CP
RP
3
10 µH
1 µF
220 nF
220 nF
3.3 Ω
4
10 µH
1 µF
220 nF
220 nF
3.3 Ω
6
15 µH
680 nF
100 nF
100 nF
4.7 Ω
8
22 µH
470 nF
100 nF
100 nF
6.2 Ω
See Figure 6.
Table 11. Theoretical table PBTL
Load
Impedance
LC Low-Pass Filter
Damping network
LF
CF
CS
CP
RP
3
10 µH
1 µF
220 nF
220 nF
2.7 Ω
4
10 µH
1 µF
220 nF
220 nF
3.3 Ω
6
15 µH
680 nF
100 nF
100 nF
6.2 Ω
8
22 µH
470 nF
100 nF
100 nF
6.2 Ω
See Figure 7.
5.2
Optimized filter
Suggest to avoid resonant peak when running amplifiers without load
Table 12. Filter optimized to minimize the peak SE
Load
impedance
LC Low-pass filter
LF
CF
CS
CP
RP
3
15 µH
680 µF
100 nF
100 nF
6.2 Ω
4
22 µH
470 nF
100 nF
100 nF
6.2 Ω
6
33 µH
330 nF
100 nF
100 nF
6.2 Ω
8
47 µH
220 nF
100 nF
100 nF
6.2 Ω
See Figure 8.
20/26
Damping network
DocID014268 Rev 5
STA510F
Output filter
Table 13. Filter optimized to minimize the peak BTL
Load
impedance
LC low-pass filter
Damping network
LF
CF
CS
CP
RP
3
10 µH
680 nF
220 nF
220 nF
3.3 Ω
4
10 µH
680 nF
220 nF
220 nF
3.3 Ω
6
15 µH
470 nF
100 nF
100 nF
4.7 Ω
8
22 µH
330 nF
100 nF
100 nF
6.2 Ω
See Figure 6.
Table 14. Filter optimized to minimize the peak PBTL
Load
impedance
LC low-pass filter
Damping network
LF
CF
CS
CP
RP
3
10 µH
680 nF
220 nF
220 nF
2.7 Ω
4
10 µH
680 nF
220 nF
220 nF
3.3 Ω
6
15 µH
470 nF
100 nF
100 nF
6.2 Ω
8
22 µH
330 nF
100 nF
100 nF
6.2 Ω
See Figure 7.
DocID014268 Rev 5
21/26
26
Package information
6
STA510F
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 24. PSSO36 (slug up) package outline
POA_7618147_A
22/26
DocID014268 Rev 5
STA510F
Package information
Table 15. PSSO36 (slug up) mechanical data
mm.
inch.
Dim.
Min.
Typ.
Max.
Min.
Typ.
Max.
A
2.15
2.47
0.084
0.097
A2
2.15
2.40
0.084
0.094
a1
0
0.075
0
0.003
b
0.18
0.36
0.007
0.014
c
0.23
0.32
0.009
0.012
10.10
10.50
0.398
0.413
7.4
7.6
0.291
0.299
D
(1)
E (1)
e
0.50
0.020
e3
8.50
0.035
F
2.3
0.090
G
0.10
0.004
G1
0.06
0.002
H
10.10
10.50
h
L
0.398
0.413
0.40
0.55
0.85
0.016
0.022
0.033
M
4.3
0.169
N
10° (max.)
10° (max.)
O
1.2
0.047
Q
0.8
0.031
S
2.9
0.114
T
3.65
0.144
U
1.0
0.039
X
4.10
4.70
0.161
0.185
Y
6.50
7.10
0.256
0.279
1. “D and E” do not include mold flash or protrusion. Mold flash or protrusion shall not exceed 0.15 mm
(0.006”).
DocID014268 Rev 5
23/26
26
Trademarks and other acknowledgments
7
Trademarks and other acknowledgments
FFX is a STMicroelectronics proprietary digital modulation technology.
ECOPACK is a registered trademark of STMicroelectronics.
24/26
DocID014268 Rev 5
STA510F
STA510F
8
Revision history
Revision history
Table 16. Document revision history
Date
Revision
13-Dec-2007
1
Initial release.
28-Jun-2011
2
Added part number STA510FTR to Table 1: Device summary
Updated ECOPACK® text in Section 6: Package information
Minor textual updates
3
Updated package to PowerSSO36 throughout datasheet
Corrected typographical error in Features
Updated Figure 1
Updated Figure 2
Updated Figure 21
03-Jun-2014
4
Added:
– Figure 5 on page 9, Figure 6 on page 10, Figure 7 on page 10 and
Figure 8 on page 11
– Section 4: Characterization curves
– Section 5: Output filter
11-Dec-2018
5
Updated Table 1: Device summary
02-Sep-2011
Changes
DocID014268 Rev 5
25/26
26
STA510F
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
26/26
DocID014268 Rev 5
工商网监
湘ICP备2023018690号
