STA515W13TR

STA515W 40 V, 3 A, quad power half bridge Datasheet - production data Description The STA515W is a monolithic quad half-bridge stage in Multipower BCD Technology. The device can be used as a dual bridge or reconfigured, by connecting pin CONFIG to pins VDD, as a single bridge with double-current capability. The device is designed, particularly, to be the output stage of a stereo all-digital high-efficiency amplifier. It is capable of delivering 10 W x 4 channels into 4  loads with 10% THD at VCC = 18 V in single-ended configuration. PowerSO36 package with exposed pad up It can also deliver 20 W + 20 W into 8  loads with 10% THD at VCC = 18 V in BTL configuration or, in single parallel BTL configuration, 40 W into a 8 load with 10% THD at VCC = 26 V. Features  Multipower BCD technology  Low input/output pulse width distortion The input pins have a threshold proportional to the voltage on pin VL.  200 m RdsON complementary DMOS output stage The STA515W comes in a 36-pin PowerSSO package with exposed pad down (EPD).  CMOS-compatible logic inputs  Thermal protection  Thermal warning output  Undervoltage protection  Short-circuit protection Table 1. Device summary Order code Ambient temp. range Package Packaging STA515W13TR 0 to 70 °C PowerSSO36 EPD Tape and reel February 2014 This is information on a product in full production. DocID11079 Rev 3 1/16 www.st.com Introduction 1 STA515W Introduction Figure 1. STA515W circuit for quad single-ended amplifiers +VCC VCC1A IN1A 29 M3 IN1A 15 17 C31 820μF L11 22μH +3.3V PWR_DN R57 10K R59 10K VL 23 CONFIG 24 PWRDN 25 FAULT 27 26 16 M2 PROTECTION & LOGIC TRISTATE C58 100nF TH_WARN M5 THWARN 28 IN1B 30 VDD 21 VDD 22 VSS 33 VSS 34 OUT1A 14 GND1A 12 VCC1B C51 1μF 11 10 M4 REGULATORS 13 7 GND1B VCC2A VCCSIG C60 100nF VCCSIG IN2A IN2A GNDREG GNDCLEAN IN2B IN2B GNDSUB 9 M15 31 20 19 M16 1 OUT2A OUT2A GND2A 4 VCC2B C52 1μF 3 5 GND2B D03AU1474bc 2/16 R42 20 C42 330pF R62 5K R63 5K L12 22μH R43 20 C43 330pF C72 100nF R52 6 C82 100nF R64 5K R65 5K DocID11079 Rev 3 C73 100nF R53 6 C83 100nF C62 100nF OUT2B OUT2B M14 C81 100nF C91 1μF 4Ω C32 820μF C92 1μF 4Ω C33 820μF L13 22μH 6 2 32 R51 6 C61 100nF 8 35 36 C41 330pF C71 100nF 1μF M17 C53 100nF R41 20 OUT1B OUT1B IN1B C58 100nF OUT1A C21 2200μF R61 5K 1μF R67 5K L14 22μH R44 20 C44 330pF R66 5K C74 100nF R54 6 C84 100nF R68 5K C93 1μF 4Ω C34 820μF C94 1μF 4Ω STA515W 2 Pin description Pin description Figure 2. Pin out GNDSUB OUT2B OUT2B VCC2B GND2B GND2A VCC2A OUT2A OUT2A OUT1B OUT1B VCC1B GND1B GND1A VCC1A OUT1A OUT1A N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 STA515W 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VCCSIG VCCSIG VSS VSS IN2B IN2A IN1B IN1A THWARN FAULT TRISTATE PWRDN CONFIG VL VDD VDD GNDREG GNDCLEAN Table 2. Pin list Pin Name Type Description 1 GNDSUB PWR 2, 3 OUT2B O 4 VCC2B PWR Positive supply 5 GND2B PWR Negative supply 6 GND2A PWR Negative supply 7 VCC2A PWR Positive supply 8, 9 OUT2A O Output half bridge 2A 10, 11 OUT1B O Output half bridge 1B 12 VCC1B PWR Positive supply 13 GND1B PWR Negative supply 14 GND1A PWR Negative supply 15 VCC1A PWR Positive supply 16, 17 OUT1A O Output half bridge 1A 18 N.C. - No internal connection 19 GNDCLEAN PWR Logical ground 20 GNDREG PWR Ground for regulator VDD 21, 22 VDD PWR 5-V regulator referred to ground 23 VL PWR High logical state setting voltage, VL Substrate ground Output half bridge 2B DocID11079 Rev 3 3/16 16 Pin description STA515W Table 2. Pin list (continued) Pin 4/16 Name Type Description 24 CONFIG I Configuration pin: 0: normal operation 1: bridges in parallel, see Parallel-output and high-current operation on page 10 25 PWRDN I Stand-by pin: 0: low-power mode 1: normal operation 26 TRISTATE I Hi-Z pin: 0: all power amplifier outputs in high-impedance state 1: normal operation 27 FAULT O Fault pin advisor (open-drain device, needs pull-up resistor): 0: fault detected (short circuit or thermal, for example) 1: normal operation 28 THWARN O Thermal-warning advisor (open-drain device, needs pull-up resistor): 0: temperature of the IC >130 oC 1: normal operation 29 IN1A I Input of half bridge 1A 30 IN1B I Input of half bridge 1B 31 IN2A I Input of half bridge 2A 32 IN2B I Input of half bridge 2B 33, 34 VSS PWR 5-V regulator referred to +VCC 35, 36 VCCSIG PWR Signal positive supply DocID11079 Rev 3 STA515W 3 Electrical characteristics Electrical characteristics Table 3. Absolute maximum ratings Symbol Parameter Value Unit VCC DC supply voltage (Pins 4, 7, 12, 15) 40 V Vmax Maximum voltage on pins 23 to 32 5.5 V Top Operating temperature range 0 to 70 °C Ptot Power dissipation (Tcase = 70 °C) 21 W Tstg, Tj Storage and junction temperature -40 to 150 °C Table 4. Recommended operating conditions Symbol Parameter Min Typ Max Unit VCC DC supply voltage (Pins 4, 7, 12, 15) 10 - 36 V VL Input logic reference 2.7 3.3 5.0 V Tamb Ambient temperature 0 - 70 °C Table 5. Thermal data Symbol Parameter Min Typ Max Unit Tj-case Thermal resistance junction to case (thermal pad) - - 1.5 °C/W TjSD Thermal shut-down junction temperature - 150 - °C Twarn Thermal warning temperature - 130 - °C thSD Thermal shut-down hysteresis - 25 - °C Unless otherwise stated, the test conditions for Table 6 below are VL = 3.3 V, VCC = 30 V, RL = 8 , fSW = 384 kHz and Tamb = 25 °C Table 6. Electrical characteristics Symbol Parameter Test conditions Min Typ Max Unit RdsON Power P-channel/N-channel MOSFET RdsON Idd = 1 A - 200 270 m Idss Power P-channel/N-channel leakage Idss VCC = 35 V - - 50 A gN Power P-channel RdsON matching Idd = 1 A 95 - - % gP Power N-channel RdsON matching Idd = 1 A 95 - - % Dt_s Low current dead time (static) see Figure 3 - 10 20 ns DocID11079 Rev 3 5/16 16 Electrical characteristics STA515W Table 6. Electrical characteristics (continued) Symbol Test conditions Min Typ Max Unit Dt_d High current dead time (dynamic) L = 22 H, C = 470 nF RL = 8 , Idd = 3.0 A see Figure 4 - 50 ns td ON Turn-on delay time Resistive load - - 100 ns td OFF Turn-off delay time Resistive load - - 100 ns tr Rise time Resistive load see Figure 3 - - 25 ns tf Fall time Resistive load see Figure 3 - - 25 ns VCC Supply operating voltage - 10 - 36 V VIN-Low Half-bridge input, low level voltage - - - VL / 2 V 300 mV VIN-High Half-bridge input, high level voltage - VL / 2 + 300 mV - V IIN-H High level input current VIN = VL - 1 - A IIN-L Low level input current VIN = 0.3 V - 1 - A IPWRDN-H High level PWRDN pin input current VL = 3.3 V - 35 - A VLow Low logical state voltage (pins PWRDN, TRISTATE) (seeTable 7) VL = 3.3 V - - 0.8 V VHigh High logical state voltage (pins PWRDN, TRISTATE) (seeTable 7) VL = 3.3 V 1.7 - - V Supply current from VCC in power down VPWRDN = 0 V - - 3 mA IFAULT Output current on pins FAULT, THWARN with fault condition Vpin = 3.3 V - 1 - mA IVCC-HiZ Supply current from VCC in 3-state VTRISTATE = 0 V - 22 - mA IVCC Supply current from VCC in operation (both channels switching) Input pulse width = 50% duty, switching frequency = 384 kHz, no LC filters - 50 - mA IOCP Overcurrent protection threshold Isc (short circuit current limit) - 3 6 - A VUVP Undervoltage protection threshold - - 7 - V tpw_min Output minimum pulse width No load 70 - 150 ns IVCCPWRDN 6/16 Parameter DocID11079 Rev 3 STA515W Electrical characteristics Table 7. Threshold switching voltage variation with voltage on pin VL Voltage on pin VL, VL VLOW max VHIGH min Unit 2.7 0.7 1.5 V 3.3 0.8 1.7 V 5.0 0.85 1.85 V Table 8. Logic truth table Pin TRISTATE Inputs as per Figure 4 Transistors as per Figure 4 Output mode INxA INxB Q1 Q2 Q3 Q4 0 x x Off Off Off Off Hi Z 1 0 0 Off Off On On Dump 1 0 1 Off On On Off Negative 1 1 0 On Off Off On Positive 1 1 1 On On Off Off Not used DocID11079 Rev 3 7/16 16 Test circuits 4 STA515W Test circuits Figure 3. Test circuit OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t DTr Duty cycle = 50% OUTxY INxY DTf R 8Ω vdc = Vcc/2 + - gnd D03AU1458 Figure 4. Current dead time test circuit High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B DTout(A) Q1 DTin(A) Q2 INA Iout=4.5A Q3 DTout(B) Rload=8Ω OUTA L67 22μ C69 470nF L68 22μ C71 470nF C70 470nF INB Iout=4.5A Q4 Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure 8/16 DocID11079 Rev 3 DTin(B) OUTB D03AU1517 STA515W 5 Application information Application information The STA515W is a dual channel H-bridge that can deliver 20 W per channel into 8  with 10% THD at VCC = 18 V with high efficiency. The STA515W converts both DDX and binary-logic-controlled PWM signals into audio power at the load. It includes a logic interface, integrated bridge drivers, high efficiency MOSFET outputs and thermal and short-circuit protection circuitry. In DDX mode, two logic-level signals per channel are used to control the high-speed MOSFET switches which drive the speaker load in a bridge configuration, according to the damped ternary modulation operation. In binary mode, both full-bridge and half-bridge modes are supported. The STA515W includes overcurrent and thermal protection as well as an undervoltage lockout with automatic recovery. A thermal warning status is also provided. Figure 5. Block diagram for DDX or binary modes INL[1,2] Logic interface and decode INR[1,2] VL PWRDN TRISTATE FAULT THWARN Protection circuit Left H-bridge OUTPL OUTNL Right H-bridge OUTPR OUTNR Regulators Figure 6. Block diagram for binary half-bridge mode INL[1,2] Logic interface and decode INR[1,2] VL PWRDN TRISTATE FAULT THWARN Protection circuit Left A bridge OUTPL Left B bridge OUTNL Right A bridge OUTPR Right B bridge OUTNR Regulators Logic interface and decode The STA515W power outputs are controlled using one or two logic-level timing signals. In order to provide a proper logic interface, pin VL must operate at the same voltage as the DDX control logic supply. DocID11079 Rev 3 9/16 16 Application information STA515W Protection circuits The STA515W includes protection circuitry for overcurrent and thermal overload conditions. A thermal warning pin (THWARN) is activated low (open-drain MOSFET) when the IC temperature exceeds 130 °C, which is in advance of the thermal shutdown protection. When a fault condition is detected an internal fault signal acts to immediately disable the output power MOSFETs, placing both H-bridges in the high-impedance state. At the same time an open-drain MOSFET connected to pin FAULT is switched on. There are two possible modes subsequent to activating a fault:  Shutdown mode: with pins FAULT (with pull-up resistor) and TRISTATE independent, an activated fault disables the device, signalling low at pin FAULT. The device may subsequently be reset to normal operation by toggling pin TRISTATE from high to low and back to high using an external logic signal.  Automatic recovery mode: This is shown in the applications circuit in Figure 7 and Figure 7 on page 11. Pins FAULT and TRISTATE are shorted together and connected to a time constant circuit comprising R59 and C58. An activated fault forces a reset on pin TRISTATE causing normal operation to resume following a delay determined by the time constant of the circuit. If the fault condition is still present, the circuit operation continues, repeating until the fault condition is removed. An increase in the time constant of the circuit produces a longer recovery interval. Care must be taken in the overall system design so as not to exceed the protection thresholds under normal operation. Power outputs The STA515W power and output pins are duplicated to provide a low-impedance path for the device bridged outputs. All duplicated power, ground and output pins must be connected for proper operation. Pins PWRDN or TRISTATE should be used to set all MOSFETS to the high-impedance state during power-up and until the logic power supply, VL, has settled. Parallel-output and high-current operation When using DDX mode, the STA515W outputs can be connected in parallel to increase the output current capability. In this configuration the device can provide 40 W into 8 . This mode of operation is enabled with pin CONFIG connected to VDD. The inputs must be combined to give INLA = INLB and INRA = INRB, then the corresponding outputs can be shorted together to give OUTLA = OUTLB and OUTRA = OUTRB. Output filter A passive 2nd-order filter is used on the STA515W power outputs to reconstruct an analog audio signal. The system performance can be significantly affected by the output filter design and choice of passive components. Filter designs for 4- and 8- loads are shown in the applications circuits of Figure 1 on page 2 for the half-bridge mode, and Figure 7 and Figure 8 on page 11 for the full bridge. 10/16 DocID11079 Rev 3 STA515W Application information Applications circuits Figure 7 below shows a typical full-bridge circuit for supplying 20 W + 20 W into 8  speakers with 10% THD at VCC = 18 V. Figure 7. Typical stereo full-bridge configuration for 20 + 20 W +VCC VCC1A IN1A 29 VL 23 M3 IN1A +3.3V CONFIG 24 PWR_DN PWRDN 25 R59 10K FAULT 27 R57 10K 16 M2 PROTECTION & LOGIC 26 TH_WARN M5 THWARN 28 IN1B 30 VDD 21 VDD 22 VSS 33 VSS 34 OUT1A 14 GND1A 12 VCC1B OUT1B M4 REGULATORS 13 GND1B 7 VCC2A VCCSIG C60 100nF VCCSIG IN2A IN2A GNDREG GNDCLEAN IN2B IN2B GNDSUB 9 36 M15 31 20 19 M16 GND2A 4 VCC2B C31 220nF 3 OUT2B OUT2B M14 1 5 C21 100nF L113 22μH C110 100nF C109 330pF R103 6 OUT2A 2 32 OUT2A 6 8Ω L19 22μH C32 220nF 8 35 C99 100nF C23 470nF C101 100nF R98 6 R100 6 R63 20 OUT1B M17 C53 100nF C20 100nF C52 330pF C31 220nF 11 C55 1000μF L18 22μH OUT1A 10 IN1B C58 100nF C30 1μF 17 TRISTATE C58 100nF 15 R104 20 C107 100nF C108 470nF C106 100nF R102 6 8Ω C111 100nF L112 22μH GND2B D00AU1148Bbc Figure 8 below shows a single-BTL configuration capable of supplying 40 W into a 4  load at 10% THD with VCC = 19 V. This result was obtained with peak power for