STA540SAN
4 x 10-watt dual/quad power amplifier
Features
High output-power capability:
– 4 x 9 W / 2 Ω at 12 V, 1 kHz, 10%
– 4 x 10 W / 4 Ω at 17 V, 1 kHz, 10%
– 2 x 26 W / 4 Ω at 14.4 V, 1 kHz, 10%
– 2 x 15 W / 8 Ω at 16 V, 1 kHz, 10%
Minimum external component count:
– No bootstrap capacitors
– No Boucherot cells
– Internally fixed gain of 20 dB
Clipwatt15
Standby function (CMOS compatible)
No audible pop during standby operations
Diagnostic facilities:
– Clip detector
– Out to GND short circuit
– Out to VS short circuit
– Soft short at turn-on
– Thermal shutdown proximity
Description
The STA540SAN contains four single-ended,
class-AB audio amplifiers assembled in a
Clipwatt15 package.
These amplifiers are used for high-quality sound
applications. Each amplifier has integrated
short-circuit and thermal protection and
diagnostic functions. Two amplifiers can be paired
up for applications requiring high power output.
Protection for
– Output AC/DC short circuit
– Soft short circuit at turn-on
Table 1.
– Thermal cut-off limiter to prevent chip from
overheating
– High inductive loads
– ESD
Device summary
Order code
STA540SAN
December 2010
Temperature range
-40 to 150 °C
Package
Clipwatt15
Doc ID 18306 Rev 1
Packaging
Tube
1/26
www.st.com
26
Contents
STA540SAN
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Test and applications board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Standard applications circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7
Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8
General structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.1
High application flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.2
Easy single-ended to bridge transition . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.3
Internally fixed gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.4
Silent turn on/off and muting/standby functions . . . . . . . . . . . . . . . . . . . . 18
8.5
Standby driving (pin 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.6
Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.7
9
2/26
8.6.1
Rail-to-rail output voltage swing with no need of bootstrap capacitors . 19
8.6.2
Absolute stability without any external compensation . . . . . . . . . . . . . . 19
Short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.7.1
Diagnostic facilities (pin 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.7.2
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.8
Handling of the diagnostic information . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.9
PCB-layout grounding (general rules) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.10
Mute function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Doc ID 18306 Rev 1
STA540SAN
10
Contents
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Doc ID 18306 Rev 1
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Block diagram
1
STA540SAN
Block diagram
Figure 1.
Block diagram
VCC2
VCC1
13
3
A1
+
1
-
IN1
OUT1
4
A2 INV
+
ST_BY
IN2
7
2
-
OUT2
5
A3
+
15
-
IN3
OUT3
12
A4 INV
+
14
-
IN4
11
10
6
SVR
4/26
Doc ID 18306 Rev 1
8
9
P_GND
S_GND
OUT4
DIAGNOSTIC
OUTPUT
D06AU1630_bc
STA540SAN
2
Pin description
Pin description
Figure 2.
Pin connection (top view)
15
OUT3
14
OUT4
13
VCC2
12
IN3
11
IN4
10
DIAG
9
S_GND
8
P_GND
7
ST_BY
6
SVR
5
IN2
4
IN1
3
VCC1
2
OUT2
1
OUT1
clp15_pins_540san_bc
Table 2.
Pin description
Pin
Name
Type
Function
1
OUT1
OUTPUT
Channel 1 output
2
OUT2
OUTPUT
Channel 2 output
3
VCC1
POWER
Power supply
4
IN1
INPUT
Channel 1 input
5
IN2
INPUT
Channel 2 input
6
SVR
INPUT
Supply voltage rejection
7
ST_BY
INPUT
Standby control pin
8
P_GND
POWER
Power ground
9
S_GND
POWER
Signal ground
10
DIAG
OUTPUT
Diagnostics
11
IN4
INPUT
Channel 4 input
12
IN3
INPUT
Channel 3 input
13
VCC2
POWER
Power supply
14
OUT4
OUTPUT
Channel 4 output
15
OUT3
OUTPUT
Channel 3 output
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Electrical specifications
STA540SAN
3
Electrical specifications
3.1
Absolute maximum ratings
Table 3.
Absolute maximum ratings
Symbol
VSmax
Parameter
Value
Supply voltage idle mode (no signal)
24
V
Supply voltage operating
22
V
Supply voltage AC-DC short safe
20
V
VSmax
-
VST_BYmax Voltage on pin ST_BY
3.2
Ptot
Total power dissipation (Tcase = 70 °C)
35
W
Tstg, Tj
Storage and junction temperature
-40 to150
°C
Top
Operating temperature
0 to 70
°C
Thermal data
Table 4.
Thermal data
Symbol
3.3
Unit
Parameter
Min
Typ
Max
Unit
Rth j-case
Thermal resistance junction to case
-
-
2.5
°C/W
Rth j-amb
Thermal resistance junction to ambient
-
-
45
°C/W
Electrical characteristics
The results in Table 5 below were measured under the conditions VS = 15 V, RL = 4 Ω,
f = 1 kHz and Tamb = 25 °C unless otherwise specified. Refer also to the test circuit in
Figure 3 on page 8
Table 5.
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
VS
Supply voltage range
-
8
-
22
V
Id
Total quiescent drain current -
-
80
150
mA
Vos
Output offset voltage
-
-250
-
250
mV
THD = 10%
6.5
7.5
-
W
THD = 10%, VS = 17 V
S.E. RL = 4 Ω
-
10
-
W
THD = 10%, VS = 17 V
BTL, RL = 8 Ω
-
20
-
W
Po
6/26
Electrical characteristics
Output power
THD
Distortion
RL = 4 Ω, Po = 0.1 to 4 W
-
0.02
-
%
ISC
Short-circuit current
-
-
3.5
-
A
Doc ID 18306 Rev 1
STA540SAN
Electrical specifications
Table 5.
Symbol
Electrical characteristics (continued)
Parameter
Test condition
Min
Typ
Max
Unit
CT
Crosstalk
f = 1 kHz
f = 10 kHz
-
70
60
-
dB
Rin
Input impedance
-
20
30
-
kΩ
Gv
Voltage gain
-
19
20
21
dB
Gv
Voltage gain match
-
-
-
0.5
dB
EN
Total output noise
Rg = 0, “A” weighted
Inverting channels:
Non-inverting channels:
-
50
20
-
µV
SVR
Supply voltage rejection
Rg = 0, f = 300 Hz,
CSVR = 470 µF
50
-
-
dB
ASB
Standby attenuation
-
80
90
-
dB
ISB
ST_BY current consumption VST_BY = 0 to 1.5 V
-
-
100
µA
VSB
ST_BY IN threshold voltage
-
-
-
1.5
V
VSB
ST_BY OUT threshold
voltage
-
3.5
-
-
V
-
50
ST_BY pin current
Play mode VST_BY = 5 V
-
IST_BY
µA
Driving current under fault -
-
5
mA
Icd off
Clipping detector output
average current
THD = 1% (1)
-
90
-
µA
Icd on
Clipping detector output
average current
THD = 5% (1)
-
160
-
µA
VDIAG
Voltage saturation on DIAG
Sink current on pin DIAG
IDIAG = 1 mA
-
-
0.7
V
TW
Thermal warning
-
-
140
-
°C
TM
Thermal muting
-
-
150
-
°C
TS
Thermal shutdown
-
-
160
-
°C
1. Pin DIAG pulled-up to 5 V with 10 kΩ
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Test and applications board
This chapter includes information about the test and applications board including the test circuit, board layout, and parts list.
Figure 3.
Test circuit
VCC
VCC
VCC
SW1
SLIDSWITCH-2.54-3P
CN7
CN-5-02P
1
1
2
2
3
PGND
R2
R1
1K8
10K
C13
DO7
ZD1
100 nF
SGND
C6
100 nF
25 V
C12
10 µF
25 V
SGND
C4
11 IN4
4
6 SVR
SGND
6
IN3
C11
47 µF
25 V
OUT2 2
OUT4 14
Diagnostics
SGND
JP2
JUMPER2X1(DIP)
CN5
CN-5-02P
1
C9 2200 µF, 25 V
2
JP3
JUMPER2X1(DIP)
C10 2200 µF, 25 V
TP
PGND
PGND
OUT3 15
DIAG
0.22uF
10
JP6
JUMPER2X1(DIP)
IN4
P_GND
5
13
CLIPWATT15
C3 0.22uF
2
OUT1 1
STA540SAN
12 IN3
PGND
CN4
CN-5-02P
1
C8 2200 µF, 25 V
IC1
5 IN2
CN1
RCA4CH_6P
VCC1 3
0.22uF
C2 0.22uF
VCC2
JP5
JUMPER2X1(DIP)
S_GND
IN2
4 IN1
9
3
C1
ST-BY 7
SGND
JP1, JP2 :
Open = SE
Closed = BTL
8
Doc ID 18306 Rev 1
1
JP1
JUMPER2X1(DIP)
SGND
IN1
CN3
CN-5-02P
1
C7 2200 µF, 25 V
2
PGND
2
C5
1000 µF
50 V
Test and applications board
8/26
4
SGND TP1
JP3, JP4 :
Open = SE
Closed = BTL
PGND
CN6
CN-5-02P
1
2
JP4
JUMPER2X1(DIP)
PGND
STA540SAN
STA540SAN
Test and applications board
Figure 4.
Component layout
Figure 5.
Component side
Figure 6.
Solder side
Doc ID 18306 Rev 1
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Test and applications board
Table 6.
STA540SAN
List of components
Components
10/26
Suggested value
Purpose
R1
10 kΩ
Standby time constant
R2
1.8 kΩ
Ripple rejection
C1, C2, C3, C4
0.22 µF
Input AC coupling
C5
0.1 µF
Voltage supply decoupling
C6
1000 µF
Voltage supply decoupling
C7, C8, C9, C10
2200 µF
Output AC coupling
C11
47 µF
Ripple rejection
C12
10 µF
Standby time constant
C13
100 nF
Ripple rejection
ZD1
10 µF
Standby time constant
Doc ID 18306 Rev 1
STA540SAN
5
Standard applications circuits
Standard applications circuits
Figure 7.
Quad stereo
10K
ST-BY
VS
10µF
100nF
4 7
IN1
3
13
1000µF
1
0.22µF
5
IN2
OUT1
2200µF
OUT2
2200µF
OUT3
2200µF
OUT4
2
0.22µF
12
IN3
2200µF
Suggested applications:
4 x 12 W at 2 Ω, 14.4 V
4 x 10 W at 4 Ω, 17 V
4 x 9 W at 2 Ω, 12 V
4 x 5 W at 4 Ω, 12 V
15
0.22µF
11
IN4
0.22µF
6
14
8
9
10
47µF
DIAGNOSTICS
D04AU1555B
P-GND S-GND
Figure 8.
Audio performance option
1
14
2
15
470 µF
470 µF
The best audio performance is obtained with the configuration where each speaker has its
own DC blocking capacitor. If the application allows a little degradation of the spatial image it
is possible to connect a couple of speakers with only one low-value DC blocking capacitor.
Figure 9.
Double bridge
10K
ST-BY
VS
100nF
10µF
IN L
0.47µF
IN R
13
7
4
Suggested applications:
3
1
5
OUT L
2
11
0.47µF
14
12
2 x 9 W at 8 Ω, 12 V
2 x 18 W at 4 Ω, 12 V
2 x 13 W at 8 Ω, 14 V
2 x 26 W at 8 Ω, 14 V
2 x 15 W at 8 Ω, 16 V
OUT R
6
47µF
1000µF
15
8
9
10
DIAGNOSTICS
D95AU1600
A dedicated evaluation board is available for this application (see Chapter 4 on page 8).
Doc ID 18306 Rev 1
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Standard applications circuits
STA540SAN
Figure 10. Stereo Bridge
10K
VS
ST-BY
10µF
IN L
100nF
7
4
3
13
1
0.22µF
IN R
2
5
2200µF
OUT
BRIDGE
12
6
8
OUT R
14
11
0.47µF
OUT L
2200µF
0.22µF
IN BRIDGE
1000µF
9
10
15
47µF
DIAGNOSTICS
D05AU1601
Suggested applications:
2 x 9 W into 2 Ω + 1 x 18 W into 4 Ω, 12 V
2 x 12 W into 2 Ω + 1 x 26 W into 4 Ω, 14.4 V
2 x 8 W into 4 Ω + 1 x 16 W into 8 Ω, 16 V
A dedicated evaluation board is available for this application (see Chapter 4 on page 8).
12/26
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STA540SAN
6
Electrical characteristics curves
Electrical characteristics curves
Figure 11. Quiescent drain current vs supply
voltage (single-ended and bridge)
Figure 12. Quiescent output voltage vs supply
voltage (single-ended and bridge)
Figure 13. Output power vs supply voltage
Figure 14. Distortion vs output power
Figure 15. Output power vs supply voltage
Figure 16. Distortion vs output power
20
Po(W)
18
S.E.
16
Rl=4ohm
14
f=1KHz
12
T.H.D=10%
10
8
T.H.D=1%
6
4
2
0
+8
+10
+12
+14
+16
+18
+20
+22
Vs(V)
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Electrical characteristics curves
STA540SAN
Figure 17. Output power vs supply voltage
Figure 18. Distortion vs output power
Figure 19. Output power vs supply voltage
Figure 20. Crosstalk vs frequency
12
Po(W)
11
S.E.
10
Rl=8ohm
9
f=1KHz
8
7
T.H.D=10%
6
5
4
T.H.D=1%
3
2
1
0
+8
+10
+12
+14
+16
Vs(V)
+18
+20
+22
+24
Figure 21. Output power vs voltage
Figure 22. Standby attenuation vs threshold
voltage
Po(W) 35
32.5
30
BTL
27.5
Rl=8ohm
25
f=1KHz
22.5
T.H.D=10%
20
17.5
15
12.5
T.H.D=1%
10
7.5
5
2.5
0
+8
+10
+12
+14
+16
+18
+20
+22
Vs(V)
14/26
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STA540SAN
Figure 23. Supply voltage rejection vs
frequency
Electrical characteristics curves
Figure 24. Total power dissipation and
efficiency vs output power
Figure 25. Total power dissipation and
efficiency vs output power
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Thermal information
7
STA540SAN
Thermal information
In order to avoid the thermal protection intervention that is placed at Tj =150 °C (thermal
muting) or Tj=160 °C (thermal shutdown), it is important to design the heatsink Rth (°C/W)
value correctly.
The parameters that influence the design are:
z
Maximum dissipated power for the device (Pdmax)
z
Maximum thermal resistance junction to case (Rth_j-case)
z
Maximum ambient temperature Tamb_max
There is also an additional term that depends on the quiescent current, Iq, but this is
negligible in this case.
Example 1: 4-channel single-ended amplifier
VCC =14.4 V, RL = 4 Ω x 4 channels, Rth_j-case = 2.5 °C/W, Tamb_max = 50 °C, Pout = 4 x 7 W
2
P dmax
V CC
= NChannel ⋅ ----------------- = 4 ⋅ 2.62 = 10.5W
2
2Π R L
The required thermal resistance for the heatsink is
150 – T amb_max
– 50- – 2.5 = 7°C/W
"" R th_c-amb = -------------------------------------- – R th_j-case = 150
--------------------P dmax
10.5
Example 2: 2-channel single-ended plus 1-channel (BTL) amplifier
VCC = 14.4 V, RL = 2 x 2 Ω (SE) + 1 x 4 Ω (BTL), Pout = 2 x 12 W + 1 x 26 W
2
P dmax
2
V CC
2V CC
= 2 ⋅ ----------------- + ---------------- = 2 ⋅ 5.25 + 10.5 = 21W
2
2
2Π R L Π R L
The required thermal resistance for the heatsink is
150 – T amb_max
– 50- – 2.5 = 2.2°C/W
"" R th_c-amb = -------------------------------------- – R th_j-case = 150
--------------------P dmax
21
Design notes on examples 1 and 2
The values found give a heatsink that is designed to sustain the maximum dissipated power.
But, as explained in the applications note AN1965, the heatsink can be smaller when a
realistic application is considered where a musical program is used.
When the average listening power concept is considered, the dissipated power is about 40%
less than the Pdmax. Therefore, in examples 1 and 2, the resulting average dissipated power
is reduced as follows:
–
Example 1: 10.5 W - 40% = 6.3 W giving Rth_c-amb = 13.4 °C/W
–
Example 2: 21 W - 40% = 12.6 W giving Rth_c-amb = 5.4 °C/W
Figure 26 below shows the power derating curve for the device.
16/26
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STA540SAN
Thermal information
Figure 26. Power derating curve
Pd(W)
30
1) Infinite
25
1
2) 3.5C/W
2
3) 5C/W
3
20
4) 7C/W
4
15
10
5
0
0
20
40
60
80
100
120
140
160
Tamb(C)
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General structure
STA540SAN
8
General structure
8.1
High application flexibility
The availability of four independent channels makes it possible to accomplish several kinds
of applications ranging from four-speaker stereo (F/R) to two-speaker bridge solutions.
When working with single-ended conditions, the polarity of the speakers driven by the
inverting amplifier must be reversed with respect to those driven by non-inverting channels.
This is to avoid phase irregularities causing sound alterations especially during the
reproduction of low frequencies.
8.2
Easy single-ended to bridge transition
The change from single-ended to bridge configurations is made simple by means of a short
circuit across the inputs (resulting in no need of additional external components).
8.3
Internally fixed gain
The gain is internally fixed to 20 dB in single-ended mode and 26 dB in bridge mode.
The advantages of this design choice are in terms of:
8.4
z
components and space saving
z
output noise, supply voltage rejection and distortion optimization.
Silent turn on/off and muting/standby functions
Standby mode can be easily activated by means of a CMOS logic level applied to pin 7
through a RC filter.
Under standby conditions, the device is turned off completely (supply current = 1 mA typical,
output attenuation = 80 dB minimum).
All on/off operations are virtually pop-free. Furthermore, at turn-on the device stays in mute
condition for a time determined by the value assigned to the SVR capacitor. In mute mode,
the device outputs are insensitive to any kind of signal that may be present at the input
terminals. In other words, any transients coming from previous stages produce no
unpleasant acoustic effects at the speakers.
8.5
Standby driving (pin 7)
Some precautions need to be taken when defining standby driving networks. Pin 7 cannot
be directly driven by a voltage source having a current capability higher than 5 mA. In
practical cases a series resistance must be inserted, giving it the double purpose of limiting
the current at pin 7 and smoothing down the standby on/off transitions. And, when done in
combination with a capacitor, prevents output pop.
A capacitor of at least 100 nF from pin 7 to S_GND, with no resistance in between, is
necessary to ensure correct turn-on.
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STA540SAN
8.6
General structure
Output stage
The fully complementary output stage is possible with the power ICV PNP component.
This novel design is based on the connection shown in Figure 27 and allows the full
exploitation of its capabilities. The clear advantages this new approach has over classical
output stages are described in the following sections.
8.6.1
Rail-to-rail output voltage swing with no need of bootstrap capacitors
The output swing is limited only by the VCEsat of the output transistors, which are in the
range of 0.3 Ω (Rsat) each.
Classical solutions adopting composite PNP-NPN for the upper output stage have higher
saturation loss on the top side of the waveform.
This unbalanced saturation causes a significant power reduction. The only way to recover
power includes the addition of expensive bootstrap capacitors.
8.6.2
Absolute stability without any external compensation
With reference to the circuit shown in Figure 27, the gain Vout/Vin is greater than unity, that
is, approximately 1+R2/R1. The DC output (VCC/2) is fixed by an auxiliary amplifier common
to all the channels.
By controlling the amount of this local feedback, it is possible to force the loop gain (A*β) to
less than unity at a frequency where the phase shift is 180 °. This means that the output
buffer is intrinsically stable and not prone to oscillation.
The above feature has been achieved even though there is very low closed-loop gain of the
amplifier.
This is in contrast with the classical PNP-NPN stage where the solution adopted for
reducing the gain at high frequencies makes use of external RC networks, namely the
Boucherot cells.
Figure 27. The new output stage
Doc ID 18306 Rev 1
19/26
General structure
8.7
STA540SAN
Short-circuit protection
Reliable and safe operation in the presence of all kinds of short circuits involving the outputs
is assured by built-in protection. Additionally, a soft short-condition is signalled out (to the
AC/DC short circuit to GND, to VS, and across the speaker) during the turn-on phase to
ensure correct operation of the device and the speakers.
This particular kind of protection acts in such a way as to prevent the device being turned on
(by ST_BY) when a resistive path (less than 16 Ω) is present between the output and GND.
It is important to have the external current source driving the ST_BY pin limited to 5 mA.
This is because the associated circuitry is normally disabled with currents >5 mA.
This extra function becomes particularly attractive when, in the single-ended configuration,
one capacitor is shared between two outputs as shown in Figure 28.
Figure 28. Sharing a capacitor
If the output capacitor Cout is shorted for any reason, the loudspeaker is not damaged.
8.7.1
Diagnostic facilities (pin 10)
The STA540SAN is equipped with diagnostic circuitry that is able to detect the following
events:
z
Clipping in the output signal
z
Thermal shutdown
z
Output fault:
–
short to GND
–
short to VS
–
soft short at turn on
The information is available across an open collector output (pin 10) through a current
sinking when the event is detected.
Figure 29. Clipping detection waveforms
A current sinking at pin 10 is provided when a certain distortion level is reached at each
output. This function initiates a gain-compression facility whenever the amplifier is
overdriven.
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STA540SAN
8.7.2
General structure
Thermal shutdown
With the thermal shutdown feature, the output (pin 10) signals the proximity of the junction
temperature to the shutdown threshold. Typically, current sinking at pin 10 starts at
approximately 10 °C before the shutdown threshold is reached.
Figure 30. Output fault waveforms
10
10
Figure 31. Fault waveforms
ST_BY PIN
VOLTAGE
2V
t
OUT TO Vs SHORT
OUTPUT
WAVEFORM
SOFT SHORT
t
OUT TO GND SHORT
Vpin 10
CORRECT TURN-ON
FAULT DETECTION
t
CHECK AT TURN-ON
(TEST PHASE)
D05AU1603
Doc ID 18306 Rev 1
SHORT TO GND
OR TO Vs
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General structure
8.8
STA540SAN
Handling of the diagnostic information
As different diagnostic information is available at the same pin (clipping detection, output
fault, thermal proximity), the signal must be handled correctly in order to discriminate the
event. This could be done by taking into account the different timing of the diagnostic output
during each case.
Normally, clip-detector signalling under faulty conditions produces a low level at pin 10.
Based on this assumption, an interface circuitry to differentiate the information is shown in
Figure 33.
Figure 32. Waveforms
ST_BY PIN
VOLTAGE
t
Vs
OUTPUT
WAVEFORM
t
Vpin 10
WAVEFORM
t
CLIPPING
D05AU1604_bc
Figure 33. Interface circuit diagram
10
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SHORT TO GND
OR TO Vs
THERMAL
PROXIMITY
STA540SAN
8.9
General structure
PCB-layout grounding (general rules)
The device has two distinct ground leads, P_GND (power ground) and S_GND (signal
ground) which are practically disconnected from each other at chip level. Correct operation
requires that P_GND and S_GND leads be connected together on the PCB layout by means
of reasonably low-resistance tracks.
For the PCB ground configuration a star-like arrangement, where the center is represented
by the supply-filtering electrolytic capacitor ground, is recommended. In such context, at
least two separate paths must be provided; one for power ground and one for signal ground.
The correct ground assignments are as follows:
8.10
z
standby capacitor (pin 7, or any other standby driving networks): on signal ground
z
SVR capacitor (pin 6): on signal ground and to be placed as close as possible to the
device
z
input signal ground (from active/passive signal processor stages): on signal ground
z
supply filtering capacitors (pins 3 and 13): on power ground. The negative terminal of
the electrolytic capacitor must be directly tied to the battery negative line and this
should represent the starting point for all the ground paths.
Mute function
If the mute function is required, it can be accessed on SVR (pin 6) as shown in Figure 34.
Figure 34. Components for layout
10K
VS
ST-BY
10µF
IN L
IN R
IN BRIDGE
0.22µF
0.47µF
13
7
4
3
2200µF
5
2
2200µF
8
470µF
OUT L
OUT R
15
12
6
R2 10K
1000µF
1
11
R1 3.3K
MUTE
5V
0
PLAY
0.22µF
100nF
9
10
14
OUT
BRIDGE
DIAGNOSTICS
D06AU1632_bc
VS = 10 to 16 V, VSVR: mute off ≥ 0.6 to 0.8, mute on ≥ 0.2 V
Using a different value for R1 than the suggested 3.3 kΩ, results in two different situations:
z
z
R1 > 3.3 kΩ:
–
Pop noise improved
–
Lower mute attenuation
R1 < 3.3 kΩ:
–
Pop noise degradation
–
Higher mute attenuation
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Package mechanical data
9
STA540SAN
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 35. Mechanical data and package dimensions
mm
inch
DIM.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
3.2
0.126
B
1.05
0.041
C
0.15
D
0.006
1.50
Weight: 1.92gr
0.061
E
0.49
0.55
0.019
0.022
F
0.67
0.73
0.026
0.029
G
1.14
1.27
1.4
0.045
0.050
0.055
G1
17.57
17.78
17.91
0.692
0.700
0.705
H1
12
H2
H3
18.6
0.732
0.781
17.9
L1
L2
0.480
19.85
L
0.704
14.55
10.7
OUTLINE AND
MECHANICAL DATA
11
0.572
11.2
0.421
0.433
L3
5.5
0.217
M
2.54
0.100
M1
2.54
0.100
0.441
Clipwatt15
0044538 G
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STA540SAN
10
Revision history
Revision history
Table 7.
Document revision history
Date
Revision
16-Dec-2010
1
Changes
Initial release
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STA540SAN
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