STA543SA

STA543SA 24W x 1 + 7W x 2 Triple Amplifier with DC Volume Control PRELIMINARY DATA Features ■ OUTPUT POWER CAPABILITY 24W x 1 + 7W x 2 @ VCC = 15V, RL = 4Ω, THD = 10% ■ LINEAR DC VOLUME CONTROL FOR EACH SINGLE CHANNEL ■ MINIMUM EXTERNAL COMPONENTS COUNT: – NO BOOTSTRAP CAPACITORS – NO BOUCHEROT CELLS – INTERNALLY FIXED GAIN (20dB SE, 26dB BTL) Clipwatt 19 ■ OVERRATING CHIP TEMPERATURE WITH SOFT THERMAL LIMITER ■ VERY INDUCTIVE LOADS ■ FORTUITOUS OPEN GND ESD ■ ST-BY FUNCTION (CMOS COMPATIBLE) ■ ■ NO AUDIBLE POP DURING ST-BY OPERATIONS Description ■ DIAGNOSTIC FACILITIES – CLIP DETECTOR – OUT TO GND SHORT – OUT TO VS SHORT – SOFT SHORT AT TURN-ON – THERMAL SHUTDOWN PROXIMITY The device is a class AB Audio amplifier assembled in the Clipwatt19 package; it is designed for high quality sound application. The STA543SA is a 3-channels audio amplifier with DC volume control dedicated for each single channel. It is a device suitable for 2.1 solution thank to its output configuration with two single ended channels and one bridge. The Short Circuit Protection, the Thermal Protection and the Diagnostics Functions are integrated in the device. Protections ■ OUPUT AC/DC SHORT CIRCUIT ■ SOFT SHORT AT TURN-ON Order codes Part number Temp range, °C Package Packing STA543SA 0 to 70 Clipwatt 19 Tube July 2005 CD00061065 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Rev 2 1/23 www.st.com 23 STA543SA Contents 1 2 3 Block diagram and Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Test board and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 4 5 2/23 Test board parts list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 Crcuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 Evaluation Board Functional Description: . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2.1 Input Cut-off frequency: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2.2 Output Cut-off frequency: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2.3 Crossover Network for SW: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 General structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 Gain Internally Fixed to 20dB in Single Ended, 26dB in Bridge . . . . . . . . . . 15 5.2 Silent Turn On/Off and Muting/Stand-by Function . . . . . . . . . . . . . . . . . . . . 15 5.3 STAND-BY DRIVING (pin9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4 Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5 Rail-to-Rail Output Voltage Swing With No Need of Bootstrap Capacitors. . 15 5.6 Absolute Stability Without Any External Compensation. . . . . . . . . . . . . . . . . 16 5.7 BUILT–IN Shortcircuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.7.1 Diagnostic Facilities (Pin 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.7.2 Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.8 Handling of the diagnostic information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.9 PCB-Layout Grounding (general rules) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CD00061065 STA543SA 6 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 Example (A): 2 channels Single Ended + 1Ch (BTL) . . . . . . . . . . . . . . . . . . 20 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 CD00061065 3/23 STA543SA 1 Block diagram and Pins description 1.1 Block diagram Figure 1. Block diagram VCC VCC 17 3 4 IN1 OUT1 1 SVR 6 VOL1 5 IN2 2 OUT2 VOL2 STBY SVR 7 9 19 OUT3+ SVR SVR 15 18 IN3 OUT3- 13 12 VOL3 11 SVR 14 8 16 VOL_OUT AMP_IN 10 SVR PW_GND S_GND 1.2 Pins description Figure 2. Pins Connections (Top view) 19 OUT3+ 18 OUT3- 17 VCC2 16 AMP_IN 15 IN3 14 VOL_OUT 13 VOL3 12 DIAG 11 S_GND 10 P_GND 9 ST_BY 8 SVR 7 VOL2 6 VOL1 5 IN2 4 IN1 3 VCC 2 OUT2 OUT1 1 D04AU1552 4/23 CD00061065 DIAG STA543SA 1 Block diagram and Pins description Table 1. Pin description N° Pin Name Pin Type Function 1 OUT1 OUTPUT Channel 1 output 2 OUT2 OUTPUT Channel 2 output 3 VCC POWER Power supply 4 IN1 INPUT Channel 1 input 5 IN2 INPUT Channel 2 input 6 VOL1 INPUT Channel 1 volume control 7 VOL2 INPUT Channel 2 volume control 8 SVR INPUT Supply Voltage Rejection 9 ST-BY INPUT Stand-by 10 P_GND POWER Power ground 11 S_GND POWER Signal Ground 12 DIAG OUTPUT Diagnostics 13 VOL3 INPUT 14 VOL_OUT OUTPUT 15 IN3 INPUT Channel 3 input 16 AMP_IN INPUT Channel 3 amplifier input 17 VCC2 POWER Power supply 18 OUT3- OUTPUT Channel 3 negative output 19 OUT3+ OUTPUT Channel 3 positive output Channel 3 volume control Channel 3 volume control output CD00061065 5/23 STA543SA 2 Electrical specifications 2 Electrical specifications 2.1 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol 18 V Vs DC Supply Voltage 20 V Ptot Total Power Dissipation (Tcase = 70°C) Storage and Junction Temperature Vctr Volume Control DC Voltage Top Operating Temperature 35 W -40 to150 °C 7 V 0 to 70 °C Value Unit Thermal data Thermal data Symbol Table 4. Unit Operating Supply Voltage Table 3. 2.3 Value Vop Tstg, Tj 2.2 Parameter Parameter Rth j-case Thermal Resistance Junction to case Max. 2 °C/W Rth j-amb Thermal Resistance Junction to ambient Max. 45 °C/W Electrical characteristics Electrical characteristics (Refer to the test circuit, VS = 15V; RL = 4Ω; f = 1kHz; Tamb = 25°C unless otherwise specified). Symbol Parameter Vs Supply Voltage Range Id Total Quiescent Drain Current Test Condition Min. Typ. 8 Single Ended Bridge THD = 10%: RL = 4Ω -250 -150 Max. Unit 18 V 150 mA 250 150 mV Vos Output Offset Voltage Po Output Power Bridge Single Ended RL = 4Ω, Single Ended, 24 7 W W Total Harmonic Distortion Po =0.1 to 4W Bridge, Po =0.1 to10W f = 1 kHz Single Ended f = 10 kHz Single Ended f = 1 kHz Bridge f = 10 kHz Bridge 0.4 0.4 % % 70 60 60 dB dB dB dB 30 kΩ THD CT Rin 6/23 Cross Talk Input Impedance Single Ended and Bridge CD00061065 55 20 STA543SA Table 4. Symbol 2 Electrical specifications Electrical characteristics (continued) (Refer to the test circuit, VS = 15V; RL = 4Ω; f = 1kHz; Tamb = 25°C unless otherwise specified). Parameter Test Condition Single Ended, Vol Ctrl (Pins 6 Maximum Voltage Gain Internally and 7) > 4.5V Gv Fixed Bridge, Vol Ctrl (pin 13) > 4.5V (**) AMin Vol Attenuation at minimum volume Vol Ctrl < 0.5V Gv EN SVR ASB Voltage Gain Match Total Output Noise Supply Voltage Rejection ISB ST-BY Current Consumption ST-BY In Threshold Voltage VSB ST-BY Out Threshold Voltage Istby ST-BY Pin Current Icd off Icd on Vdiag Clipping Detector Output Average Current Clipping Detector Output Average Current Voltage Saturation on DIAG Typ. Max. Unit 19 25 20 26 21 27 dB dB 80 dB Single Ended f = 20 to 22 kHz (play, max. volume) Single Ended Bridge f = 20 to 22 kHz (play, max. attenuation) Single Ended Bridge Rg = 0; f = 300Hz Stand-by Attenuation VSB Min. 0.5 500 600 µV 250 500 µV 50 80 dB dB 90 VST-BY = 0 to 1.5V dB 100 µA 1.5 V 3.5 V Play Mode Vstby = 5V 50 µA Max Driving Current Under Fault 5 mA d = 1% (*) 90 µA d = 5% (*) 160 µA Sink Current at DIAG = 1mA 0.7 V TW Thermal Warning 140 °C TM Thermal Muting 150 °C TS Thermal Shut-down 160 °C Note: (*) DIAG Pulled-up to 5V with 10 kΩ; RL = 4Ω (**) For channel 3: if used the input pin 16 (with 100nF decoupling) instead of pin 15 the voltage gain is always max. and it is independent from Volume Control. CD00061065 7/23 STA543SA 3 Test board and Layout 3 Test board and Layout Figure 3. Test board Figure 4. PC boards and component layout Component layout Solder side Component side 8/23 CD00061065 STA543SA Figure 5. 3 Test board and Layout Test circuit ST-BY 1 2 3 R4 10K ON OFF VS + C9 +5V C10 10µF 25V + C11 0.1µF 1000µF 25V 3 VCC VCC 9 STBY 17 PGND +5V IN1 R1 270K VOL. P1 CONTR.1 50K IN1 6 VOL1 5 IN2 7 VOL2 JP1 C12 OUT1 1 2200µF 25V OUT1 C2 0.1µF C3 0.22µF IN2 R2 270K P2 VOL. CONTR.2 50K PGND JP2 C13 OUT2 2200µF 25V + +5V 2 OUT2 C4 C5 0.22µF IN3 270K IN3 13 VOL3 14 VOL_OUT 16 AMP_IN JP3 C14 OUT3+ 19 2200µF 25V OUT3 (OUT3+) C6 0.1µF JP4 PGND C7 0.22µF C15 OUT3- 18 2200µF 25V + IN4 OUT4 (OUT3-) JP6 DIAG 12 10 + SVR S_GND 8 PW_GND C8 47µF 25V SGND 11 R3 JP5 15 + 0.1µF +5V P3 VOL. CONTR.3 50K 4 + +5V IC1 STA540SA - STA543SA C1 0.22µF DIAG CD00061065 9/23 STA543SA 3 Test board and Layout 3.1 Test board parts list Table 5. Components Suggested Value R1, R2, R3 300kΩ DC Volume CTRL R4 10kΩ ST-BY TIME CONSTANT P1, P2, P3 100kΩ DC Vol. -CTRL C2, C4, C6 0.1µF Vol. -CTRL Bypass C1,C3,C5,C7 0.22µF INPUT DC DECOUPLING C8 47µF RIPPLE REJECTION C9 10µF ST-BY TIME CONSTANT C10 0.1µF SUPPLY VOLTAGE BYPASS C11 1000µF SUPPLY VOLTAGE BYPASS C12,C13 2200µF OUTPUT DC DECOUPLING Table 6. 10/23 Test board parts list Purpose Jumper selection Jumpers Purpose Connection JP1, JP2, JP3 DC Volume CTRL Closed JP4 Volume CTRL OUT Closed JP5, JP6 Bypass DC out Capacitors Closed connect BTL speaker Between Out 3+ And Out 3- CD00061065 STA543SA 4 4 Evaluation Board Evaluation Board In addition to the Test Board shown in Figure 3. intended also to evaluate the STA540SA Amplifier, it is possible to order the dedicated STA543SA evaluation board of Figure 6. The PCB layout (single layer) is shown in Figure 7. 4.1 Crcuit description With this board it is possible to amplify three analog signals Left, Right, Subwoofer coming from separated sources or to generate the BASS part to be sent to the Subwoofer via a passive crossover network. All the three channels have a Linear DC volume Control. Figure 6. Evaluation Board Schematic +5V R1 10K +5V VS + C1 C2 10µF 25V + C3 100nF 1000µF 25V C4 3 17 GND VCC N.M. VCC2 R2 ST_BY U1 9 ST-BY SGND 0.22µF IN1(L) 4 IN1 6 VOL1 +5V R3 SGND 300K OUT1 + R4 100K VOL. CONTR. 1 1 C6 C5 OUTL 1000µF 25V P1 N.M. 100nF 100K VOL. CONTR. 2 R5 300K 7 VOL2 5 IN2 PGND C7 0.22µF R7 N.M. N.M. IN3(SW) C10 0.47µF R8 300K P2 100K VOL. CONTR. 3 + 2 C9 OUTR 1000µF 25V IN3 13 VOL3 OUT3+ 19 OUT3+ 14 VOL_OUT OUT3- 18 OUT3- 16 AMP_IN PGND C12 100nF +5V C13 1µF +5V DIAG SVR 12 + 47µF 25V S_GND 8 C14 11 N.M. OUT2 15 C11 P_GND C8 10 R6 STA543SA 100nF +5V IN2(R) R9 10K DIAG CD00061065 11/23 STA543SA 4 Evaluation Board Figure 7. Evaluation Board PCB and Component Layout Component Layout Table 7. PCB Part list Component Recommended Value Larger than Purpose Smaller then Recommended value Recommended value Larger On/Off time Smaller On/Off time Larger On/Off time Smaller On/Off time R1 10K St-By Circuit R2,R7 Not mounted See notes R3,R6 Not mounted See notes R4,R5,R8 300K DC-Vol CTRL P1,P2 100K pot. DC-Vol CTRL R10 10K Open Collector Pull up C1 10uF St-by Circuit C2 100nF Supply Voltage Bypass Danger of oscillations C3 1000uF Supply Voltage Bypass Danger of oscillations C4,C8 220nF Input DC decoupling L/R Lower low freq Cutoff Higher low freq Cutoff C10 470nF Input DC decoupling Bass Lower low freq Cutoff Higher low freq Cutoff C11 Not mounted See notes C6,C7,C12 100nF DC Vol. bypass C5,C9 1000uF Output Dc decoupling Lower low freq Cutoff Higher low freq Cutoff C13 1uF C14 47uF SVR Increase of SVR , increase of switch ON time Degradation of SVR 12/23 CD00061065 STA543SA 4 Evaluation Board 4.2 Evaluation Board Functional Description: 4.2.1 Input Cut-off frequency: The input Cut-off frequency is set by the external capacitor (C4,C8,C10) values and by the internal Input Impedance Rin ( 30KΩ typ) fi (cut-off) = 1 / 2π ( Ri x Ci) for the suggested values we have Left/Right f i = 1 / 2π (30KΩ x 220nF) = 24Hz SW fi = 1 / 2π (30KΩ x 470nF) = 11Hz 4.2.2 Output Cut-off frequency: The output Cut-off frequency is set by the DC decoupling capacitor placed in series to the speaker (C5,C9) value and by the Speaker Impedance 4.2.3 C5,C9 8ohm 6ohm 4ohm Unit 100uF 199 265 398 Hz 220uF 90 121 181 Hz 470uF 42 56 85 Hz 1000uF 20 27 40 Hz 2200uF 9 12 18 Hz Crossover Network for SW: with this board it's possible, when the Bass Audio Signal to be sent to CH.3 is not available from the Audioprocessor, to generate it with a simple Low Pass Filter composed by an RC network. The components to be added are R3,R6,C11: fo = 1 / 2π R3 (R4) x C11 example: for R3 = R4 = 4K7 we have C11 = 100nF → 340Hz C11 = 220nF → 150Hz C11 = 330nF → 100Hz It is advisable at this point to modify the value of the DC decoupling capacitors in such a way to send to L and R speakers only the high frequencies. For example the frequency response shown in Figure 8. was obtained with Rl = 8ohm, C5=C9= 100uF, R3=R6= 4K7 and C11=220nF Note: In order to give the input freq response less sensitive to the spread in the Input Impedance (Rin parameter) , it is possible to add externally two resitors R2,R7 in parallel to Rin. CD00061065 13/23 STA543SA 4 Evaluation Board Figure 8. Frequency response +20 +15 +10 SW L/R +5 +0 -5 d B r A -10 -15 -20 R3=R6= 4k7 -25 -30 C11= 220nF -35 C5=C9= 100uF -40 Rl= 8ohm -45 -50 10 20 50 100 200 500 Hz 14/23 CD00061065 1k 2k 5k 10k 20k STA543SA 5 General structure 5 General structure 5.1 Gain Internally Fixed to 20dB in Single Ended, 26dB in Bridge Advantages of this design choice are in terms of: 5.2 ● components and space saving ● output noise, supply voltage rejection and distortion optimization. Silent Turn On/Off and Muting/Stand-by Function The stand-by can be easily activated by means of a CMOS level applied to pin 9 through a RC filter. Under stand-by condition the device is turned off completely (supply current = 1mA typ.; output attenuation= 80dB min.). Every ON/OFF operation is virtually pop free. Furthemore, at turn-on the device stays in muting condition for a time determined by the value assigned to the SVR capacitor. While in muting the device outputs becomes insensitive to any kinds of signal that may be present at the input terminals. In other words every transient coming from previous stages produces no unplesantacoustic effect to the speakers. 5.3 STAND-BY DRIVING (pin9) Some precautions have to be taken in the definition of stand-by driving networks: pin 9 cannot be directly driven by a voltage source whose curent capability is higher than 5mA. In pratical cases a series resistance has always to be inserted, having it the double purpose of limiting the current at pin 9 and to smooth down the stand-by ON/OFF transitions - in combination with a capacitor - for output pop prevention. In any case, a capacitor of at lest 100nF from pin 9 to S-GND, with no resistance in between, is necessary to ensure correct turn-on. 5.4 Output Stage The fully complementary output stage was made possible by the development of a new component: the ST exclusive power ICV PNP. A novel design based upon the connection shown in Figure 9. has then allowed the full exploitation of its possibilities. The clear advantages this new approach has over classical output stages are as follows: 5.5 Rail-to-Rail Output Voltage Swing With No Need of Bootstrap Capacitors. The output swing is limited only by the VCEsat of the output transistors, which are in the range of 0.3Ω (Rsat) each. CD00061065 15/23 STA543SA 5 General structure Classical solutions adopting composite PNP-NPN for the upper output stage have higher saturation loss on the top side of the waveform. This unbalanced saturation causes a significant power reduction. The only way to recover power consists of the addition of expensive bootstrap capacitors. 5.6 Absolute Stability Without Any External Compensation. Referring to the circuit of Figure 9. the gain Vout/Vin is greater than unity, approximately 1+R2/ R1. The DC output (VCC/2) is fixed by an auxiliary amplifier common to all the channels. By controlling the amount of this local feedback it is possible to force the loop gain (A*β) to less than unity at frequency for which the phase shift is 180°. This means that the output buffer is intrinsically stable and not prone to oscillation. Most remarkably, the above feature has been achieved in spite of the very low closed loop gain of the amplifier. In contrast, with the classical PNP-NPN stage, the solution adopted for reducing the gain at high frequencies makes use of external RC networks, namely the Boucherot cells. Figure 9. 5.7 The new output stage BUILT–IN Shortcircuit Protection Reliable and safe operation, in presence of all kinds of short circuit involving the outputs is assured by BUILT-IN protectors. Additionally to the AC/DC short circuit to GND, to VS, across the speaker, a SOFT SHORT condition is signalled out during the TURN-ON PHASE so assuring correct operation for the device it self and for the loudspeaker. This particular kind of protection acts in such a way to avoid the device is turned on (by ST-BY) when a resistive path (less than 16 ohms) is present between the output and GND. As the involved circuitry is normally disabled when a current higher than 5mA is flowing into the ST-BY pin, it is important, in order not to disable it, to have the external current source driving the STBY pin limited to 5mA. 16/23 CD00061065 STA543SA 5.7.1 5 General structure Diagnostic Facilities (Pin 12) The STA543SA is equipped with a diagnostic circuitry able to detect the following events: ● Clipping in the output signal ● Thermal shutdown ● Output fault: – short to GND – short to VS – soft short at turn on The information is available across an open collector output (pin 12) through a current sinking when the event is detected Figure 10. Clipping Detection Waveforms A current sinking at pin 12 is provided when a certain distortion level is reached at each output. This function allows gain compression facility whenever the amplifier is overdriven. 5.7.2 Thermal Shutdown In this case the output 12 will signal the proximity of the junction temperature to the shutdown threshold. Typically current sinking at pin 12 will start ~10°C before the shutdown threshold is reached. Figure 11. Output fault waveforms CD00061065 17/23 STA543SA 5 General structure Figure 12. Fault waveforms ST-BY PIN VOLTAGE 2V t OUT TO Vs SHORT OUTPUT WAVEFORM SOFT SHORT t OUT TO GND SHORT CORRECT TURN-ON FAULT DETECTION Vpin 12 t CHECK AT TURN-ON (TEST PHASE) 5.8 D05AU1603 SHORT TO GND OR TO Vs Handling of the diagnostic information As different kinds of information is available at the same pin (clipping detection, output fault, thermal proximity), this signal must be handled properly in order to discriminate the event. This could be done taking into account the different timing of the diagnostic output during each case. Normally the clip detector signalling produces a low level at out 12 that present under faulty conditions: based on this assumption an interface circuitry to differentiate the information is the represented in the schematic of Figure 14. Figure 13. Waveforms ST-BY PIN VOLTAGE t Vs OUTPUT WAVEFORM t Vpin 12 WAVEFORM t CLIPPING D05AU1604 18/23 CD00061065 SHORT TO GND OR TO Vs THERMAL PROXIMITY STA543SA 5 General structure Figure 14. 5.9 PCB-Layout Grounding (general rules) The device has 2 distinct ground leads, P-GND (POWER GROUND) and S-GND (SIGNAL GROUND) which are practically disconnected from each other at chip level. Proper operation requires that P-GND and S-GND leads be connected together on the PCB-layout by means of reasonably low-resistance tracks. As for the PCB-ground configuration, a star-like arrangement whose center is represented by the supply-filtering electrolytic capacitor ground is highly advisable. In such context, at least 2 separate paths have to be provided, one for P-GND and one for S-GND. The correct ground assignments are as follows: – STANDBY CAPACITOR, pin 9 (or any other standby driving networks): on S-GND – SVR CAPACITOR (pin 8): on S-GND and to be placed as close as possible to the device. – INPUT SIGNAL GROUND (from active/passive signal processor stages): on S-GND. – SUPPLY FILTERING CAPACITORS (pins 3,17): on P-GND. The (-) terminal of the electrolytic capacitor has to be directly tied to the battery (-) line and this should represent the starting point for all the ground paths. CD00061065 19/23 STA543SA 6 Thermal Information 6 Thermal Information In order to avoid the thermal protection intervention that is placed at Tj=150°C (Thermal Muting) or Tj=160°C (Thermal Shut-down), it is important the Heat Sinker RTH (°C/W) dimensioning. The parameters that influence the dimensioning are: ● Maximum dissipated power for the device (Pd max) ● Max.Thermal resistance Junction to case (RTHj-c) ● Max. Ambient temperature Tamb. Max There is also an additional term that depends on the Iq (quiescent current). 6.1 Example (A): 2 channels Single Ended + 1Ch (BTL) VCC= 14.4V, Rload = 2x 4Ω (SE) + 1x 4Ω (BTL) Pout = 2 x 7W + 1 x 24W 2 2 2Vcc Vcc P d ma x = 2 ⋅ ------------------ + ----------------- = 2 ⋅ 2.62 + 10.5 = 15.76W 2 2 2π R1 π R1 150 – T a mbmax 150 – 50 (Heat sink) RTHc-a = --------------------------------------- – R TH j – c = ---------------------- – 2 = 4.3 °C/W P dm ax 15.76 NOTE: The values found gives an heatsinker that is dimensioned to sustain the max. dissipated power, but as explained in the Application Note (AN1965) the heatsinker can be smaller when we consider the real application where a musical program is used. If we consider the so called "Average Listening Dissipated Power" concept we obtain a value that is about 40% less respect the Pdmax (see AN1965 for reference). So in the examples (A) and we will obtain the value for the Average Listening Dissipated Power that is respectively: -Example (A) : 15.76 W - 40% = 9.45W that gives RTHc-a = 8.5°C/W In Figure 15. is shown the Power Derating curve for the device Figure 15. Power Derating Curve Pd(W) 30 1) Infinite 25 1 2) 3.5°C/W 2 3 20 3) 5C/W 4) 7C/W 4 5) 10C/W 15 10 5 5 0 0 20 40 60 80 Tamb (°C) 20/23 CD00061065 100 120 140 160 STA543SA 7 7 Package information Package information Figure 16. Clipwatt 19 Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 3.2 0.126 B 1.05 0.041 C 0.15 0.006 D 1.50 0.061 E 0.49 0.55 0.019 0.022 F 0.47 0.50 0.58 0.018 0.020 G 0.87 1.00 1.13 0.034 0.039 0.044 G1 17.87 18.0 18.13 0.703 0.708 0.713 F1 0.1 H1 H3 0.004 12.0 H2 0.480 18.6 0.732 19.85 0.781 L 17.9 0.704 L1 14.55 0.572 L2 10.7 OUTLINE AND MECHANICAL DATA 11.0 11.2 0.421 0.433 L3 5.50 0.217 M 2.54 0.100 M1 2.54 0.100 0.441 Clipwatt19 7390917 A CD00061065 21/23 STA543SA 8 Revision history 8 22/23 Revision history Date Revision Changes 12-July-2005 1 Initial release. 28-July-2005 2 Modified figgs 6 and 7. CD00061065 STA543SA Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com CD00061065 23/23