STAC2942B
Datasheet
HF/VHF/UHF RF power N-channel MOSFET
Features
1
1
2
3
3
STAC780-4B
Pin connection
Pin
Connection
1
Drain
2
Source (bottom side)
3
Gate
Order code
Frequency
VDD
POUT
Gain
Efficiency
STAC2942BW
175 MHz
50 V
350 W
21 dB
60 %
•
•
•
•
Gold metallization
Excellent thermal stability
Common source push-pull configuration
POUT = 350 W min. with 21 dB gain at 175 MHz
•
•
In compliance with the 2002/95/EC European directive
ST air-cavity STAC packaging technology
Description
The STAC2942B is a gold metallized N-channel MOS field-effect RF power transistor,
intended for use in 50 V DC large signal applications up to 250 MHz.
Product status link
STAC2942B
Product summary
Order code
STAC2942BW
Marking
STAC2942
Package
STAC780-4B
Packing
Box
Base / Bulk qty
20 / 80
DS6158 - Rev 8 - April 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
STAC2942B
Electrical data
1
Electrical data
1.1
Maximum ratings
Table 1. Absolute maximum ratings (TCASE = 25 °C)
Symbol
V(BR)DSS(1)
VDRG(1)
VGS
ID
PDISS
TJ
TSTG
Parameter
Value
Unit
Drain source voltage
130
V
Drain-gate voltage (RGS = 1 MΩ)
130
V
Gate-source voltage
±20
V
Drain current
40
A
Power dissipation
625
W
Maximum operating junction temperature
200
°C
-65 to +150
°C
Value
Unit
0.28
°C/W
Storage temperature range
1. TJ = 150 °C
1.2
Thermal data
Table 2. Thermal data
Symbol
RthJC
1.3
Parameter
Junction-case thermal resistance
ESD protection characteristics
Table 3. ESD protection
Symbol
HBM
DS6158 - Rev 8
Test Methodology
Human Body Model (per JESD22-A114)
Class
2
page 2/16
STAC2942B
Electrical characteristics
2
Electrical characteristics
( TCASE = +25 °C, unless otherwise specified)
2.1
Static
Table 4. Static (per side)
Symbol
V(BR)DSS
2.2
Parameter
Drain - Source Breakdown
voltage
Test conditions
VGS = 0 V, IDS = 100 mA,
TJ = 150 °C
Min.
Typ.
Max.
130
Unit
V
IDSS
Zero gate voltage drain
Leakage Current
VGS = 0 V, VDS = 50 V
100
μA
IGSS
Gate - Source leakage
current
VGS = 20 V, VDS = 0 V
250
nA
VGS(Q)
Gate quiescent voltage
VDS = 10 V, ID = 250 mA
4.0
V
VDS(ON)
Drain - Source on voltage
VGS = 10 V, ID = 10 A
3
V
GFS
Forward transconductance
VDS = 10 V, ID = 5 A
CISS
Input capacitance
COSS
Ouput capacitance
CRSS
Reverse transfer capacitance
1.5
2.5
5
VDS = 50 V, f = 1 MHz
S
425
pF
202
pF
12
pF
Dynamic
Table 5. Dynamic (1)
Symbol
POUT
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Output power
PIN = 4 W
350
450
-
W
ŋD
Drain efficiency
PIN = 4 W
60
75
-
%
VSWR
Load mismatch
POUT = 350 W, all phases
angles
5:1
1. F = 175 MHz, VDD = 50 V, IDQ = 2 X 250 mA.
DS6158 - Rev 8
page 3/16
STAC2942B
Impedance
3
Impedance
Figure 1. Current conventions
GADG170720191138MT
Table 6. Impedance data
Note:
DS6158 - Rev 8
Freq. (MHz)
ZIN (Ω)
ZDL(Ω)
175
2.0 - j2.0
3.5 + j 5.2
Measured gate-to-gate and drain-to-drain, respectively, balanced configuration.
page 4/16
STAC2942B
Typical performance
4
Typical performance
Figure 2. Capacitances versus drain supply voltage
Figure 3. Output power versus drain supply voltage
AM00556v1
1000
Output power (W)
Capacitances (pF)
800
Ciss
Crss
Coss
600
500
A M 0 0 5 5 6 v 1 .s v g
400
500
Pin = 1.25 W
450
Pin = 5 W
Pin = 2.5 W
400
350
300
250
200
300
150
200
100
100
50
0
0
10
20
30
40
Supply voltage (V)
50
0
60
Figure 4. Output power versus gate voltage
20
30
F = 175 MHz
Pin = 2.4 W
VDD = 50 V
IDQ = 2 x 250 mA
AM00559v1
650
350
550
500
Output power (W)
400
300
250
Tcase = + 25 °C
200
150
450
VDD = 50 V
400
VDD = 40 V
350
300
250
Tcase = + 80 °C
200
Tcase = - 20 °C
150
100
F = 175 MHz
IDQ = 2 x 250 mA
Tcase = + 25 °C
100
50
50
0
0
-1
-0.5
0
0.5
1
1.5
2
Gate voltage (V)
2.5
3
0
3.5
Figure 6. Output power vs input power and case
temperature
2
4
6
8
10
Input power (W)
12
14
16
Figure 7. Efficiency vs output power and case
temperature
AM00560v1
650
AM00561v1
100
600
F = 175 MHz
VDD = 50 V
IDQ = 2 x 250 mA
90
550
80
500
70
450
Efficiency (%)
Output power (W)
60
600
450
400
350
F = 175 MHz
300
VDD = 50 V
IDQ = 2 x 250 mA
250
200
60
50
40
Tcase = + 25 °C
30
150
100
50
Tcase = + 25 °C
20
Tcase = +80 °C
10
Tcase = +80 °C
Tcase = - -20 °C
Tcase = - -20 °C
0
0
0
DS6158 - Rev 8
40
50
Supply voltage (V)
Figure 5. Output power versus input power
AM00558v1
500
Output power (W)
F = 175 MHz, IDQ = 2 x 250 mA
550
900
700
AM00557v1
600
F = 1 MHz
2
4
6
8
10
Input Power (W)
12
14
16
0
100
200
300
400
500
Output power (W)
600
700
page 5/16
STAC2942B
Typical performance
Figure 8. Power gain vs output power and case temperature
AM00562v1
23
22
21
Power gain (dB)
20
F = 175 MHz
VDD = 50 V
IDQ = 2 x 250 mA
19
18
17
16
Tcase = + 25 °C
15
Tcase = +80 °C
14
Tcase = - -20 °C
13
0
50 100 150 200 250 300 350 400 450 500 550 600 650
Output power (W)
Figure 9. Safe operating area
Tcase = +25°C / Tj = +200°C
Max Drain Current- Id (A)
1000
100
DC
10 mS
1 mS
10
1
1100
1
1100
00
1000
Drain supplyvoltage - Vdd(V)
AM07221v1
Figure 10. Transient thermal impedance
0.30
0.25
Zthj-c (°C/W)
Single pulse
0.1
0.20
0.2
0.3
0.15
0.4
0.5
0 10
0.6
0.7
0.8
0.05
1.E-04
0.9
1.E-03
1.E-02
1.E-01
1.E+00
Rectangula r powe r pulse width (s)
AM07222v1
DS6158 - Rev 8
page 6/16
STAC2942B
Typical performance
Figure 11. Transient thermal model
R
R7
R =0. 0156223
R
R8
R =. 04686695
R
R6
R =. 1309871
R
R5
R =. 0865236
O hm
C
C8
C =0. 0025604
F
O hm
C
C7
C =0. 0025604
F
O hm
C
C6
C =0. 0377893
F
O hm
C
C5
C =0. 2418993
F
AM06109v1
DS6158 - Rev 8
page 7/16
STAC2942B
Test circuit
5
Test circuit
5.1
Electrical schematic and BOM
Figure 12. 175 MHz test circuit schematic (production test circuit)
B
A
A
B
B
C
A
A
A
A
A
C
DIMENSION TABLE
DIM
C
B
0.056" SPACE
A
C
IN
MM
A
B
0.430
0.950
10.92
24.13
C
2.500
63.50
TRANSMISSION LINE DIMENSIONS
50V
FB6
C25
FB3
R6
C21
C2
T1
CORE
B1
FB1
T1
C1
FB2
C28
CORE
LI
C15
D.U.T.
T2
CORE
C23
FB5
R4
R2
C5
C6
C9
CORE
+Vgg
C10
C19
C18
C17
C13
C11
T2
C12
C16
B2
C29
FB2
+Vgg
R5
FB4
C14
R1
R3
C22
C20
C24
NOTES:
1. DIMENSIONS AT COMPONENT SYMBOLS ARE REFERENCE FOR COMPONENT PLACEMENT. SEE SHEET 1.
2. GAP BETWEEN GROUND & TRANSMISSION LINES IS 0.056[1.42]
TYP
AM00528v1
DS6158 - Rev 8
page 8/16
STAC2942B
Electrical schematic and BOM
Table 7. 175 MHz test circuit component list
Component
C1, C2, C14,
C15, C24, C25
DS6158 - Rev 8
Description
1200 pF ATC 700B chip capacitor
C5
75 pF ATC 100B chip capacitor
C6
ST406 variable capacitor
C9, C10
47 pF ATC 100B chip capacitor
C11, C12, C13
43 pF ATC 100B chip capacitor
C16, C18
470 pF ATC 100B chip capacitor
C17, C19, C20, C21
10,000 pF ATC 200B chip capacitor
C22, C23
0.1 μF 200 V chip capacitor
C28
10 μF 100 V electrolytic capacitor
C29
0.8 - 8 pF variable capacitor
R1, R2, R5, R6
430 Ω, 1/2 W chip resistor
R3, R4
270 Ω 1/2 W axial lead resistor
B1
RG-316 50 Ω 11.8" through ferrite toroid
B2
RG-142 50 Ω 11.8"
T1
4:1, RG-316 25 Ω, 5.9", 2 turns thru ferrite core
T2
1:4, 25 Ω semi-rigid cable, OD .141", 5.9"
L1
λ/4 inductor, RG-142 50 Ω, 11.8", 3 turns thru ferrite toroid
FB1,FB5
Ferrite toroid
FB2, FB6
Multi-aperture core
FB3, FB4
Surface mount ferrite bead
PCB
Rogers ultralam 2000, Er 2.55, .060"
page 9/16
STAC2942B
Test circuit layout
5.2
Test circuit layout
Figure 13. Test circuit
DS6158 - Rev 8
page 10/16
STAC2942B
Package information
6
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
6.1
STAC780-4B package information
Figure 14. STAC780-4B package outline
DM00481937 rev.2
DS6158 - Rev 8
page 11/16
STAC2942B
STAC780-4B package information
Table 8. STAC780-4B mechanical data
Symbol
DS6158 - Rev 8
Milimeters
Min
Typ
Max
A
3.76
3.86
A1
5.03
5.13
B
4.57
5.08
C
9.65
9.91
D
17.78
18.08
E
33.88
34.19
F
0.13
0.18
G
0.97
1.14
H
1.52
1.70
I
4.83
5.33
J
9.52
9.78
K
27.69
28.19
L
3.20
3.25
3.30
M
3.43
3.51
3.58
M
3.30
3.38
3.45
p
7.14
7.21
7.29
q
1.45
R1
0.64
R2
1.52
r
1.52
s
0.51
Θ
10°
CH1
2.03
CH2
1.52
page 12/16
STAC2942B
Marking information
6.2
Marking information
Figure 15. Marking information
LEGEND
PACKAGE FACE
: TOP
Marking Composition Field
A - MARKING AREA
B - ST LOGO
C - Assy Plant
(PP)
D - BE Sequence
(LLL)
A
B
C
F
D
E
G
H I
E - Diffusion Traceability Plant
(WX)
F - COUNTRY OF ORIGIN
(MAX CHAR ALLOWED = 3)
G - Test & Finishing Plant
(TF)
H - Assy Year
(Y)
I - Assy Week
(WW)
DS6158 - Rev 8
page 13/16
STAC2942B
Revision history
Table 9. Document revision history
Date
Version
Changes
20-Mar-2009
1
First release.
16-Apr-2010
2
Added Figure 10, Figure 11 and Figure 12.
12-Aug-2011
3
05-Sep-2011
4
Update figures on coverpage and Section 6: Package mechanical data.
Inserted Section 7: Marking, packing and shipping specifications.
Update L and M dimensions Table 8 on page 13.
Updated order code in Table 1: Device summary and Table 9: Packing and shipping
specifications.
11-Oct-2011
5
Updated Table 10: Marking specifications and Figure 16: Marking layout.
Modified document title.
DS6158 - Rev 8
17-Jan-2012
6
Updated Table 5: Dynamic new “load mismatch” has been inserted.
27-Jan-2014
7
Modified pin labeling in Figure 1: Pin connection.
03-Apr-2020
8
Updated package information. Added Section 1.3 ESD protection characteristics.
page 14/16
STAC2942B
Contents
Contents
1
2
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
1.1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3
ESD protection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1
Static. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2
Dynamic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
4
Typical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
6
5.1
Electrical schematic and BOM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2
Test circuit layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6.1
STAC780-4B package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.2
Marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
DS6158 - Rev 8
page 15/16
STAC2942B
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
DS6158 - Rev 8
page 16/16