STAP16DPPS05
Automotive-grade low voltage 16-bit constant current LED sink
driver with output error detection and auto power-saving
Datasheet - production data
designed for LED panel displays. The device
contains a 16-bit serial-in, parallel-out shift
register that feeds a 16-bit D-type storage
register. In the output stage, sixteen regulated
current sources are designed to provide 3 to
40 mA of constant current to drive the LEDs.
Features
AECQ100 qualified
Low voltage power supply down to 3 V
16 constant current output channels
Adjustable output current through external
resistor
Short and open output error detection
Serial data IN/parallel data OUT
3.3 V micro driver-able
Auto power-saving
Output current: 3 - 40 mA
Auto power-saving
Max. clock frequency: 30 MHz
20 V current generator rated voltage
Power supply voltage: from 3 V to 5.5 V
Thermal shutdown for overtemperature
protection
ESD protection 2.0 KV HBM
Applications
Dashboard and infotainment backlighting
Exterior/interior lighting
DTRLs
The STAP16DPPS05 features the open and
short LED detection on the outputs. The
detection circuit checks 3 different conditions
which may occur on the output line: short to
GND, short to VO or open line. The data detection
results are loaded in the shift register and shifted
out via the serial line output. The detection
functionality is implemented without increasing
the pin number through a secondary function of
the output enable and latch pin (DM1 and DM2
respectively). A dedicated logic sequence allows
the device to enter or leave detection mode.
Through an external resistor, users can adjust
the output current of the STP16DPPS05 thus
controlling the light intensity of the LEDs. In
addition, the user can adjust the intensity of the
brightness of the LED’s from 0 % to 100 %
through the OE/DM2 pin. The auto power
shutdown and auto power-ON feature allows the
device to save power with no external
intervention. The STAP16DPPS05 guarantees a
20 V output driving capability, allowing users to
connect more LEDs in series. The high clock
frequency, 30 MHz also satisfies the system
requirement of high volume data transmission.
The 3.3 V of voltage supply is very useful for
applications interfacing any microcontroller from
3.3 V micro. Compared with a standard TSSOP
package, the TSSOP exposed pad increases the
capability of heat dissipation by a factor of 2.5.
Description
The STAP16DPPS05 is a monolithic, low
voltage, low current power 16-bit shift register
Table 1: Device summary
Order code
Package
Packing
STAP16DPPS05XTTR
TSSOP24 (exposed pad)
2500 parts per reel
November 2017
DocID024306 Rev 7
This is information on a product in full production.
1/29
www.st.com
Contents
STAP16DPPS05
Contents
1
Summary description ...................................................................... 3
1.1
2
Pin connections and description........................................................ 3
Electrical ratings ............................................................................. 4
2.1
Absolute maximum ratings ................................................................ 4
2.2
Thermal data ..................................................................................... 4
2.3
Recommended operating conditions ................................................. 5
3
Electrical characteristics ................................................................ 6
4
Equivalent circuit and outputs ....................................................... 8
5
Timing diagrams ............................................................................ 11
6
Typical characteristics .................................................................. 14
7
Error detection mode functionality .............................................. 18
8
9
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7.1
Phase one: entering error detection mode ...................................... 18
7.2
Phase two: error detection .............................................................. 19
7.3
Phase three: resuming normal mode .............................................. 21
7.4
Error detection conditions ............................................................... 21
7.5
Auto power-saving .......................................................................... 23
Package information ..................................................................... 24
8.1
TSSOP24 exposed pad package information ................................. 25
8.2
TSSOP24 packing information ........................................................ 27
Revision history ............................................................................ 28
DocID024306 Rev 7
STAP16DPPS05
1
Summary description
Summary description
Table 2: Typical current accuracy
Current accuracy
Output voltage
≥ 1.3 V
1.1
Between bits
Between ICs
±1%
±2%
Output current
VDD
Temperature
5 to 40 mA
3.3 V to 5 V
25 °C
Pin connections and description
Figure 1: Pin connection
The exposed pad is electrically connected to a metal layer electrically isolated or
connected to ground.
Table 3: Pin description
Pin n°
Symbol
Name and function
1
GND
Ground terminal
2
SDI
Serial data input terminal
3
CLK
Clock input terminal
4
LE/DM1
Latch input terminal - detect mode 1 (see operation principle)
5-20
OUT-15
Output terminal
21
OE/DM2
Input terminal of output enable (active low) - detect mode 1
(see operation principle)
22
SDO
Serial data out terminal
23
R-EXT
Input terminal for an external resistor for constant current programming
24
VDD
Supply voltage terminal
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Electrical ratings
STAP16DPPS05
2
Electrical ratings
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 4: Absolute maximum ratings
Symbol
2.2
Parameter
Value
Unit
Vdd
Supply voltage
0 to 7
V
VO
Output voltage
-0.5 to 20
V
IO
Output current
50
mA
VI
Input voltage
-0.4 to Vdd
V
IGND
GND terminal current
800
mA
fCLK
Clock frequency
50
MHz
TOPR
Operating temperature range
-40 to +150
°C
TSTG
Storage temperature range
-55 to +150
°C
Value
Unit
37.5
°C/W
Thermal data
Table 5: Thermal data
Symbol
Rthj-amb
Parameter
Thermal resistance
junction-ambient (1)
TSSOP24 (exposed pad) (2)
Notes:
(1)According
(2)The
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to JEDEC standard 51-7B.
exposed pad should be soldered to the PCB in order to derive the thermal benefits.
DocID024306 Rev 7
STAP16DPPS05
2.3
Electrical ratings
Recommended operating conditions
Table 6: Recommended operating conditions
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
3.0
-
5.5
V
-
20
V
-
40
mA
VDD
Supply voltage
VO
Output voltage
IO
Output current
OUTn
IOH
Output current
SeriaL-OUT
-
+1
mA
IOL
Output current
Serial-OUT
-
-1
mA
VIH
Input voltage
0.7 VDD
-
VDD
V
VIL
Input voltage
-0.3
-
0.3 VDD
V
3
twLAT
LE/DM1 pulse width
20
-
ns
twCLK
CLK pulse width
10
-
ns
100
-
ns
twEN
OE/DM2
pulse width
VDD = 3.0 V to 5.0 V
tSETUP(D)
Setup time for DATA
8
-
ns
tHOLD(D)
Hold time for DATA
5
-
ns
tSETUP(L)
Setup time for LATCH
8
-
ns
fCLK
Clock frequency
Cascade operation
(1)
-
30
MHz
Notes:
(1)If
the device is connected in cascade, it may not be possible to achieve the maximum data transfer. Please
consider the timings carefully.
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Electrical characteristics
3
STAP16DPPS05
Electrical characteristics
VDD = 5 V, Tj = -40 °C to 125 °C, unless otherwise specified.
Table 7: Electrical characteristics
Symbol
Parameter
VIH
Input voltage high level
0.7·VDD
VDD
VIL
Input voltage
low level
GND
0.3·VDD
VOL
Test condition
IOL = + 1 mA
VOH
Serial data output voltage
(SDO)
IOH
Output leakage current
Min.
Typ.
Max.
0.03
0.4
Vo =19 V, OUTn = OFF
0.5
2
VDD = 3.3 V, VO = 0.3 V,
Rext = 3.9 kΩ
±1
±5
VDD = 3.3 V, VO = 0.6 V,
Rext = 980 Ω
±0.5
±4
ΔIOL3
VDD = 3.3 V, VO = 1.3 V,
Rext = 490 Ω
±0.5
±4
ΔIOL2
VDD = 3.3 V, VO = 0.6 V,
Rext = 980 Ω
±5
VDD = 3.3 V, VO = 1.3 V,
Rext = 490 Ω
±6
ΔIOL1
ΔIOL2
ΔIOL3
Current accuracy
channel-to-channel (1)(2)
Current accuracy deviceto-device(1)
IOH = - 1 mA
Pull-up resistor for OE pin
150
300
600
RIN(down)
Pull-down resistor for LE
pin
100
200
400
Rext = 980 Ω, OE = low,
OUT0 to OUT7 = OFF
200
300
Rext = 980 Ω, OE = high,
OUT0 to OUT7 = ON
5
7.5
IDD(OFF2)
Rext = 490 Ω, OE = high,
OUT0 to OUT15 = ON
8
11
IDD(ON1)
Rext = 980 Ω, OE = low,
OUT0 to OUT15 = ON
6
7.5
Rext = 490 Ω, OE = low,
OUT0 to OUT15 = ON
8
11
IDD(OFF1)
Supply current (OFF)
Supply current (ON)
IDD(ON2)
Tsd
Thermal shutdown(3)
V
VDD-0.4
RIN(up)
IDD(AutoOff)
Unit
µA
%
kΩ
µA
mA
170
°C
Notes:
(1)Test
performed with all outputs turned on, but only one output loaded at a time.
(2)∆
IOL+
= ((IOLmax - IOLmean) / IOLmean) * 100, ∆IOL - = ((IOLmin - IOLmean) / IOLmean)*100, where IOLmean = (IOLout1+IOLout2+…+IOLout16) /
16.
(3)Not
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tested, guaranteed by design.
DocID024306 Rev 7
STAP16DPPS05
VDD = 5 V, Tj = 25 °C, unless otherwise specified.
Electrical characteristics
Table 8: Switching characteristics
(all table limits are guaranteed by design. Not tested in production.)
Symbol
fclk
Parameter
Clock frequency
Test condition
LE/DM1 = H,
OE/DM2
tPLH2
tPLH3
=L
OE/DM2 - OUTn ,
LE\\DM1 = H
tPLH
CLK-SDO
CLK OUTn ,
tPHL1
LE/DM1 = H,
OE/DM2
=L
LE/DM1- OUTn ,
VIH = VDD
VIL = GND
IO = 20 mA
RL = 60 Ω
CL = 10 pF
VL = 3.0 V
tPHL2
OE/DM2
tPHL3
Max.
Unit
30
MHz
VDD = 3.3 V
55
90
VDD = 5 V
30
50
VDD = 3.3 V
48
80
VDD = 5 V
30
45
VDD = 3.3 V
70
120
VDD = 5 V
45
65
VDD = 3.3 V
21
35
VDD = 5 V
15
25
VDD = 3.3 V
28
35
VDD = 5 V
22
40
VDD = 3.3 V
13
35
VDD = 5 V
12
18
VDD = 3.3 V
24
35
VDD = 5 V
21
30
VDD = 3.3 V
24
40
VDD = 5 V
17
25
=L
OE /DM2- OUTn ,
LE/DM1 = H
tPHL
CLK-SDO
Output fall time
10~90 % of voltage
waveform
VDD = 3.3 V
30
55
tON
VDD = 5 V
10
20
Output rise time
90~10 % of voltage
waveform
VDD = 3.3 V
4
10
tOFF
VDD = 5 V
3
8
tr
tf
CLK rise time (1)
CLK fall
ns
=L
LE/DM1- OUTn ,
OE/DM2
Typ.
Cascade operation
CLK- OUTn ,
tPLH1
Min.
5
time(1)
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Notes:
(1)If
devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer
between two cascaded devices.
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Equivalent circuit and outputs
4
STAP16DPPS05
Equivalent circuit and outputs
Figure 2: OE/DM2 terminal
Figure 3: LE/DM1 terminal
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STAP16DPPS05
Equivalent circuit and outputs
Figure 4: CLK, SDI terminal
Figure 5: SDO terminal
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Equivalent circuit and outputs
STAP16DPPS05
Figure 6: Block diagram
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DocID024306 Rev 7
STAP16DPPS05
5
Timing diagrams
Timing diagrams
Table 9: Truth table
OUT0 ............. OUT7 ................
Clock
LE/DM1
OE/DM2
Serial-IN
SDO
OUT15
_|¯
H
L
Dn
Dn ..... Dn - 7 ..... Dn -15
Dn - 15
_|¯
L
L
Dn + 1
No change
Dn - 14
_|¯
H
L
Dn + 2
Dn + 2 ..... Dn - 5 ..... Dn -13
Dn - 13
¯|_
X
L
Dn + 3
Dn + 2 ..... Dn - 5 ..... Dn -13
Dn - 13
¯|_
X
H
Dn + 3
OFF
Dn - 13
OUTn = ON when Dn = H OUTn = OFF when Dn = L.
Figure 7: Timing diagram
Latch and output enable terminals are level-sensitive and are not synchronized
with rising or falling edge of LE/DM1 signal. When LE/DM1 terminal is low level,
the latch circuit holds previous set of data. When LE/DM1 terminal is high level,
the latch circuit refreshes new set of data from SDI chain. When OE/DM2
terminal is at low level, the output terminals Out 0 to Out 15 respond to data in the
latch circuits, either ‘1’ ON or ‘0’ OFF. When OE/DM2 terminal is at high level,
all output terminals are switched OFF.
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Timing diagrams
STAP16DPPS05
Table 10: Enable IO: shutdown truth table
Clock
LE/DM1
SDI0........... SDI7............ SDI15
SH
Auto power-up
OUTn
_|¯
H
All = L
Active
Not active(1)
OFF
_|¯
L
No change
No change
No change
No change
_|¯
H
One or more = H
Not active
Active
X(2)
Notes:
(1)At
power-up, the device starts in shutdown mode.
(2)Undefined.
Figure 8: Clock, serial-in, serial-out
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STAP16DPPS05
Timing diagrams
Figure 9: Clock, serial-in, latch, enable, outputs
Figure 10: Outputs
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Typical characteristics
6
STAP16DPPS05
Typical characteristics
Figure 11: Output current vs REXT resistor
Table 11: Output current vs REXT resistor
REXT (Ω)
Output current (mA)
23700
1
11730
2
6930
3
4090
5
2025
10
1000
20
667
30
497
40
331
60
Conditions:
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temperature = 25 °C, VDD = 3.3 V; 5.0 V, ISET = 3 mA; 5 mA; 10 mA; 20 mA; 50 mA;
60 mA.
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STAP16DPPS05
Typical characteristics
Figure 12: ISET vs dropout voltage (Vdrop)
Table 12: ISET vs dropout voltage (Vdrop)
Iout (mA)
Avg (mV) @ 3.3 V
Avg (mV) @ 5.0 V
3
36
37
5
71
72
10
163
163
20
346
347
40
724
726
60
1080
1110
TA = 25 °C, VDD = 3.3 V; 5 V.
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Typical characteristics
STAP16DPPS05
Figure 13: Output current vs ± ΔIOL(%)
Figure 14: Idd ON/OFF
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DocID024306 Rev 7
STAP16DPPS05
Typical characteristics
Figure 15: Power dissipation vs package temperature
The exposed pad should be soldered to the PCB to obtain the thermal benefits.
Figure 16: Turn-ON output current characteristics(1)
Figure 17: Turn-OFF output current characteristics(2)
Notes:
(1)The
reference level for the TON characteristics is 50 % of OE/DM2 signal and 90 % of output current.
(2)The
reference level for the TOFF characteristics is 50 % of OE/DM2 signal and 10 % of output current.
Electrical conditions:
VDD = 3.3 V, Vin = VDD, Vled = 3.0 V, RL = 60 Ω, CL = 10 pF.
Ch1 (yellow) = OE/DM2, Ch2 (blue) = SDI, Ch3 (purple) = VOUT, Ch4 (green) = OUT.
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Error detection mode functionality
STAP16DPPS05
7
Error detection mode functionality
7.1
Phase one: entering error detection mode
From the “normal mode” condition the device can switch to “error mode” by a logic
sequence on the OE/DM2 and LE/DM1 pins, as shown in the following table and
diagram:
Table 13: Entering error detection mode - truth table
CLK
1°
2°
3°
4°
5°
OE/DM2
H
L
H
H
H
LE/DM1
L
L
L
H
L
Figure 18: Entering error detection mode - timing diagram
After these five CLK cycles, the device goes into the “error detection mode” and at the 6 th
rising edge of the CLK, the SDI data are ready for sampling.
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STAP16DPPS05
7.2
Error detection mode functionality
Phase two: error detection
The 16 data bits must be set to “1” in order to set ON all the outputs during detection. The
data are latched by LE/DM1 and after that the outputs are ready for the detection process.
When the microcontroller switches the OE/DM2 to LOW, the device drives the LEDs in
order to analyze if an OPEN or SHORT condition has occurred.
Figure 19: Detection diagram
The LED status is detected in 1 microsecond (minimum) and after this time the
microcontroller sets OE/DM2 in HIGH state and the output data detection results go to
the microprocessor via SDO.
Detection mode and normal mode both use the same data format. As soon as all the
detection data bits are available on the serial line, the device may go back to normal mode
of operation. To re-detect the status, the device must go back in normal mode and re-enter
error detection mode.
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Error detection mode functionality
STAP16DPPS05
Figure 20: Timing example for open and/or short-circuit detection
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STAP16DPPS05
7.3
Error detection mode functionality
Phase three: resuming normal mode
The sequence for re-entering normal mode is shown in the following table:
Table 14: Resuming normal mode - timing diagram
CLK
1°
2°
3°
4°
5°
OE/DM2
H
L
H
H
H
LE/DM1
L
L
L
L
L
For proper device operation, the “entering error detection” sequence must be
followed by a “resume mode” sequence, it is not possible to insert consecutive
equal sequences.
7.4
Error detection conditions
Table 15: Detection conditions (VDD = 3.3 to 5 V, temperature range -40 to 125 °C)
Configuration
Detect mode
Detection results
SW-1 or
SW-3b
Open line or output short to
GND detected
==> IODEC ≤ 0.5 x IO
No error
detected
==> IODEC ≥ 0.5 x IO
SW-2 or
SW-3a
Short on LED or short to VLED detected
==> VO ≥ 2.6 V
No error
detected
==> VO ≤ 2.3 V
Where: IO = the output current programmed by the REXT, IODEC = the detected
output current in detection mode.
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Error detection mode functionality
STAP16DPPS05
Figure 21: Detection circuit
Figure 22: Error detection sequence
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STAP16DPPS05
7.5
Error detection mode functionality
Auto power-saving
The auto power-saving feature minimizes the quiescent current if no active data is detected
on the latches and auto powers-up the device as the first active data is latched.
Figure 23: Auto power-saving feature
Conditions:
Temp. = 25 °C, VDD = 3.3 V, Vin = VDD, VLed = 3.0 V, Iset = 20 mA
Ch1 (yellow) = CLK, Ch2 (blue) = SDI, Ch3 (purple) = LE/DM1, Ch4 (green) = IDD
Idd consumption:
Idd (normal operation) = 2.93 mA
Idd (shutdown condition) = 170 µA
Figure 24: Auto power-saving feature: first output TON
Conditions:
Temp. = 25 °C, VDD = 3.3 V, Vin = VDD, VLed = 3.0 V, Iset = 20 mA
Ch1 (yellow) = CLK, Ch2 (blue) = SDI, Ch3 (purple) = LE/DM1, Ch4 (green) = IDD
When the device goes from auto power-saving to normal operating condition, the
first output switching ON shows the T ON condition as seen in the plot above.
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Package information
8
STAP16DPPS05
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
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8.1
Package information
TSSOP24 exposed pad package information
Figure 25: TSSOP24 exposed pad package outline
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Package information
STAP16DPPS05
Table 16: TSSOP24 exposed pad mechanical data
mm
Dim.
Min.
Max.
A
1.20
A1
0.15
A2
0.80
b
0.19
0.30
c
0.09
0.20
1.00
1.05
D
7.70
7.80
7.90
D1
4.80
5.00
5.2
E
6.20
6.40
6.60
E1
4.30
4.40
4.50
E2
3.00
3.20
3.40
e
L
0.65
0.45
L1
k
060
0.75
1.00
0°
aaa
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Typ.
8°
0.10
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STAP16DPPS05
8.2
Package information
TSSOP24 packing information
Figure 26: TSSOP24 reel outline
Table 17: TSSOP24 tape and reel mechanical data
mm
Dim.
Min.
A
Typ.
Max.
-
330
13.2
C
12.8
-
D
20.2
-
N
60
-
T
-
22.4
Ao
6.8
-
7
Bo
8.2
-
8.4
Ko
1.7
-
1.9
Po
3.9
-
4.1
P
11.9
-
12.1
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Revision history
9
STAP16DPPS05
Revision history
Table 18: Document revision history
Date
Revision
21-May-2013
1
Initial release.
01-Jul-2013
2
Added footnote in Table 8: Switching characteristics.
11-Oct-2013
3
Modified TOPR value in Table 4: Absolute maximum ratings.
10-Mar-2014
4
Modified footnote 1 in Table 8: Switching characteristics.
Added footnote 2 in Table 8: Switching characteristics.
Updated Table 1: Pin connections and Table 3: Pin description.
05-Jun-2014
5
Updated Table 16: TSSOP24 exposed pad mechanical data.
Minor text changes.
10-Nov-2015
6
Updated features in cover page.
Minor text changes.
07-Nov-2017
7
Changes
Updated title in cover page.
Updated Figure 5: "SDO terminal", Figure 8: "Clock, serial-in, serialout" , Figure 9: "Clock, serial-in, latch, enable, outputs" and Section 8:
"Package information".
Minor text changes.
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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST
products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
design of Purchasers’ products.
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© 2017 STMicroelectronics – All rights reserved
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