STB100NF04T4

STB100NF04T4, STP100NF04 Automotive-grade N-channel 40 V, 4.3 mΩ typ., 120 A STripFET™ II Power MOSFET in a D²PAK and TO-220 Datasheet packages - production data Features TAB Order code VDS RDS(on) max. ID Ptot STB100NF04T4 40 V 4.6 mΩ 120 A 300 W STP100NF04 40 V 4.6 mΩ 120 A 300 W TAB D2PAK TO-220 1 2 3     AEC-Q101 qualified Exceptional dv/dt capability 100% avalanche tested Low gate charge Applications Figure 1: Internal schematic diagram  D(2, TAB) Switching applications Description These Power MOSFETs have been developed using STMicroelectronics’ unique STripFET process, which is specifically designed to minimize input capacitance and gate charge. This renders the devices suitable for use as primary switch in advanced high-efficiency isolated DCDC converters for telecom and computer applications, and applications with low gate charge driving requirements. G(1) S(3) AM01475v1_Tab Table 1: Device summary Order code Marking Package Packing STB100NF04T4 B100NF04 D²PAK Tape and reel STP100NF04 P100NF04 TO-220 Tube November 2016 DocID9969 Rev 7 This is information on a product in full production. 1/20 www.st.com Contents STB100NF04T4, STP100NF04 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Spice thermal model ..................................................................... 10 4 Test circuits ................................................................................... 11 5 Package information ..................................................................... 12 6 2/20 5.1 D²PAK packing information ............................................................. 12 5.2 D²PAK packing information ............................................................. 15 5.3 TO-220 package information ........................................................... 17 Revision history ............................................................................ 19 DocID9969 Rev 7 STB100NF04T4, STP100NF04 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 40 V VGS Gate- source voltage ±20 V ID (1) Drain current (continuous) at TC = 25°C 120 A ID (1) Drain current (continuous) at TC=100°C 120 A Drain current (pulsed) 480 A Total dissipation at TC = 25°C 300 W 6 V/ns 1.2 J - 55 to 175 °C IDM (2) PTOT dv/dt(3) EAS (4) Peak diode recovery voltage slope Single pulse avalanche energy Tj Operating junction temperature range Tstg Storage temperature range Notes: (1)Current (2)Pulse (3)I SD limited by package width limited by safe operating area. ≤120 A, di/dt ≤300A/μs, VDD =V(BR)DSS, Tj ≤ TJMAX (4)Starting Tj = 25 °C, ID = 60 A, VDD = 30 V. Table 3: Thermal data Symbol Parameter Value D²PAK Rthj-case Rthj-pcb (1) Rthj-amb Thermal resistance junction-ambient TO-220 0.5 Thermal resistance junction-case Thermal resistance junction-pcb Unit °C/W 35 °C/W 62.5 °C/W Notes: (1)When mounted on a 1-inch² FR-4 board, 2oz Cu. DocID9969 Rev 7 3/20 Electrical characteristics 2 STB100NF04T4, STP100NF04 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4: On/off states Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions Min. ID = 250 µA, VGS = 0 V 40 Typ. Max. Unit V VDS = 40 V, VGS = 0 V 1 µA IDSS Zero gate voltage drain current VDS = 40 V, VGS = 0 V TC = 125°C(1) 10 µA IGSS Gate body leakage current VGS = ±20 V, VDS = 0 V ±100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 4 V RDS(on) Static drain-source on- resistance VGS = 10 V, ID= 50 A 4.3 4.6 mΩ Min. Typ. Max. Unit - 5100 pF - 1300 pF - 160 pF VDD = 32 V, ID = 120 A , VGS = 10 V (see Figure 21: "Test circuit for gate charge behavior") - 110 - 35 nC - 70 nC VDD = 20 V, ID = 60 A , RG = 4.7 Ω ,VGS = 10 V (see Figure 20: "Test circuit for resistive load switching times" and Figure 25: "Switching time waveform") - 35 ns - 220 ns - 80 ns - 50 ns 2 Notes: (1)Defined by design,not subject to production test Table 5: Dynamic Symbol Ciss Test conditions Input capacitance VDS = 25 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge td(on) Turn-on delay time tr td(off) tf 4/20 Parameter Rise time Turn-off delay time Fall time DocID9969 Rev 7 150 nC STB100NF04T4, STP100NF04 Electrical characteristics Table 6: Source drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 120 A ISDM(1) Source-drain current (pulsed) - 480 A VSD(2) Forward on voltage ISD = 120 A, VGS = 0 V - 1.3 V Reverse recovery time ISD = 120 A, VDD = 20 V, di/dt = 100 A/μs V, Tj = 150 °C (see Figure 22: "Test circuit for inductive load switching and diode recovery times") - 75 - ns - 185 - nC - 5 - A tr td(off) Reverse recovery charge tf Reverse recovery current Notes: (1) Pulse width limited by safe operating area. (2)Pulsed: Pulse duration = 300 μs, duty cycle 1.5% DocID9969 Rev 7 5/20 Electrical characteristics 2.1 Electrical characteristics (curves) Figure 2: Power dissipation vs. temperature Figure 3: Max Id current vs. temperature Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Transconductance 6/20 STB100NF04T4, STP100NF04 Figure 7: Static drain-source on-resistance DocID9969 Rev 7 STB100NF04T4, STP100NF04 Electrical characteristics Figure 8: Gate charge vs. gate-source voltage Figure 9: Capacitance variations Figure 10: Normalized gate threshold voltage vs. temperature Figure 11: Normalized on-resistance vs. temperature Figure 12: Source-drain diode forward characteristics Figure 13: Normalized BVDSS vs. temperature DocID9969 Rev 7 7/20 Electrical characteristics STB100NF04T4, STP100NF04 Figure 14: Thermal resistance Rthj-pcb vs. PCB copper area Figure 15: Thermal impedance Figure 16: Max power dissipation vs. PCB copper area 8/20 DocID9969 Rev 7 Figure 17: Safe operating area STB100NF04T4, STP100NF04 Electrical characteristics Figure 18: Allowable Iav vs. time in avalanche The previous curve give the safe operating area for unclamped inductive loads, single pulse or repetitive, under the following conditions: PD(AVE) = 0.5*(1.3*BVDSS*IAV) EAS(AR)= PD(AVE)*TAV Where: IAV is the allowable current in avalanche PD(AVE) is the average power dissipation in avalnche(single pulse) tAV is the time in avalanche To de rate above 25°C, at fixed IAV, the following equation must be applied: IAV= 2*(Tjmax-TCASE)/(1.3*BVDSS*Zth) Where: Zth= K*Rth is the value coming from normalized thermal response at fixed pulse width equal to TAV DocID9969 Rev 7 9/20 Spice thermal model 3 STB100NF04T4, STP100NF04 Spice thermal model Figure 19: Spice model schematic Table 7: Spice parameter 10/20 Parameter Node Value CTHERM1 5-4 0.011 CTHERM1 4-3 0.0012 CTHERM3 3-2 0.05 CTHERM4 2-1 0.1 RTHERM1 5-4 0.09 RTHERM2 4-3 0.02 RTHERM3 3-2 0.11 RTHERM4 2-1 0.17 DocID9969 Rev 7 STB100NF04T4, STP100NF04 4 Test circuits Test circuits Figure 20: Test circuit for resistive load switching times Figure 21: Test circuit for gate charge behavior Figure 22: Test circuit for inductive load switching and diode recovery times Figure 23: Unclamped inductive load test circuit Figure 24: Unclamped inductive waveform DocID9969 Rev 7 Figure 25: Switching time waveform 11/20 Package information 5 STB100NF04T4, STP100NF04 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 5.1 D²PAK packing information Figure 26: D²PAK (TO-263) type A package outline 0079457_A_rev22 12/20 DocID9969 Rev 7 STB100NF04T4, STP100NF04 Package information Table 8: D²PAK (TO-263) type A package mechanical data mm Dim. Min. Typ. Max. A 4.40 4.60 A1 0.03 0.23 b 0.70 0.93 b2 1.14 1.70 c 0.45 0.60 c2 1.23 1.36 D 8.95 9.35 D1 7.50 7.75 8.00 D2 1.10 1.30 1.50 E 10 E1 8.50 8.70 8.90 E2 6.85 7.05 7.25 e 10.40 2.54 e1 4.88 5.28 H 15 15.85 J1 2.49 2.69 L 2.29 2.79 L1 1.27 1.40 L2 1.30 1.75 R V2 0.4 0° DocID9969 Rev 7 8° 13/20 Package information STB100NF04T4, STP100NF04 Figure 27: D²PAK (TO-263) recommended footprint (dimensions are in mm) 14/20 DocID9969 Rev 7 STB100NF04T4, STP100NF04 5.2 Package information D²PAK packing information Figure 28: Tape outline DocID9969 Rev 7 15/20 Package information STB100NF04T4, STP100NF04 Figure 29: Reel outline Table 9: D²PAK tape and reel mechanical data Tape Reel mm mm Dim. 16/20 Dim. Min. Max. A0 10.5 10.7 A B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 F 11.4 11.6 N 100 K0 4.8 5.0 T P0 3.9 4.1 P1 11.9 12.1 Base quantity 1000 P2 1.9 2.1 Bulk quantity 1000 R 50 T 0.25 0.35 W 23.7 24.3 DocID9969 Rev 7 Min. Max. 330 13.2 26.4 30.4 STB100NF04T4, STP100NF04 5.3 Package information TO-220 package information Figure 30: TO-220 type A package outline DocID9969 Rev 7 17/20 Package information STB100NF04T4, STP100NF04 Table 11: TO-220 type A mechanical data mm Dim. Min. Max. A 4.40 4.60 b 0.61 0.88 b1 1.14 1.55 c 0.48 0.70 D 15.25 15.75 D1 18/20 Typ. 1.27 E 10.00 10.40 e 2.40 2.70 e1 4.95 5.15 F 1.23 1.32 H1 6.20 6.60 J1 2.40 2.72 L 13.00 14.00 L1 3.50 3.93 L20 16.40 L30 28.90 øP 3.75 3.85 Q 2.65 2.95 DocID9969 Rev 7 STB100NF04T4, STP100NF04 6 Revision history Revision history Table 12: Document revision history Date Revision Changes 23-Mar-2005 2 New template 01-Mar-2006 3 Removed I²PAK and inserted D²PAK. 04-Sep-2006 4 New template,no content change 20-Feb-2007 5 Typo mistake on page 1 16-Mar-2013 6 Minor text changes – Modified: Figure 17 – Updated: Section 4: Package mechanical data and Section 5: Packaging mechanical data 21-Nov-2016 7 Updated title in cover page. Updated Section 2: "Electrical characteristics". Minor text changes. DocID9969 Rev 7 19/20 STB100NF04T4, STP100NF04 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 20/20 DocID9969 Rev 7