STB120N10F4

STB120N10F4, STP120N10F4 N-channel 100 V, 8 mΩ typ., 120 A, STripFET™ DeepGATE™ Power MOSFETs in D2PAK and TO-220 packages Datasheet − production data Features Order codes VDS RDS(on) max. ID 100 V 10 mΩ 120 A TAB STB120N10F4 TAB STP120N10F4 3 3 1 1 2 D PAK 2 • N-channel enhancement mode • Very low on-resistance • Low gate charge TO-220 • 100% avalanche rated Applications Figure 1. Internal schematic diagram • Switching applications Description 'Ć7$% These devices are N-channel Power MOSFETs developed using ST’s STripFET™ DeepGATE™ technology. The devices have a new gate structure and are specially designed to minimize on-state resistance to provide superior switching performance. * 6 $0Y Table 1. Device summary Order codes Marking Packages Packaging D2PAK Tape and reel TO-220 Tube STB120N10F4 120N10F4 STP120N10F4 April 2014 This is information on a product in full production. DocID026168 Rev 1 1/18 www.st.com Contents STB120N10F4, STP120N10F4 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Test circuits ............................................... 8 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 D2PAK, STB120N10F4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 TO-220, STP120N10F4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/18 DocID026168 Rev 1 STB120N10F4, STP120N10F4 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 100 V VGS Gate-source voltage ± 20 V ID Drain current (continuous) at TC = 25 °C 120 A ID Drain current (continuous) at TC = 100 °C 85 A Drain current (pulsed) 390 A Total dissipation at TC = 25 °C 300 W 2 W/°C 215 mJ – 55 to 175 °C IDM (1) PTOT Derating factor EAS (2) Tstg Tj Single pulse avalanche energy Storage temperature Max. operating junction temperature 1. Pulse width limited by safe operating area 2. Starting Tj = 25 °C, ID= 65 A, VDD= 50 V Table 3. Thermal data Value Symbol Parameter Rthj-case Thermal resistance junction-case max Rthj-pcb Thermal resistance junction-pcb max Rthj-amb Thermal resistance junction-ambient max DocID026168 Rev 1 Unit D2PAK TO-220 0.5 °C/W 35 °C/W 62.5 °C/W 3/18 18 Electrical characteristics 2 STB120N10F4, STP120N10F4 Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 4. On/off states Symbol Parameter V(BR)DSS Drain-source Breakdown voltage Test conditions ID = 250 μA, VGS = 0 Min. Typ. Max. 100 Unit V VDS = 100 V 1 μA VDS = 100 V,TC=125 °C 100 μA Gate-body leakage current (VDS = 0) VGS = ± 20 V ±100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 μA 4 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 60 A 8 10 mΩ Min. Typ. Max. Unit - 7290 - pF - 568 - pF - 387 - pF - 131 - nC - 40 - nC - 37 - nC Min. Typ. Max. Unit VDD = 50 V, ID = 60 A RG = 4.7 Ω VGS = 10 V (see Figure 13) - 32 - ns - 116 - ns VDD = 50 V, ID = 60 A, RG = 4.7 Ω, VGS = 10 V (see Figure 13) - 111 - ns - 79 - ns IDSS IGSS Zero gate voltage Drain current (VGS = 0) 2 Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS = 25 V, f = 1 MHz, VGS = 0 VDD = 50 V, ID = 120 A, VGS = 10 V (see Figure 14) Table 6. Switching times Symbol td(on) tr td(off) tf 4/18 Parameter Turn-on delay time Rise time Turn-off-delay time Fall time Test conditions DocID026168 Rev 1 STB120N10F4, STP120N10F4 Electrical characteristics Table 7. Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 120 A ISDM (1) Source-drain current (pulsed) - 390 A VSD (2) Forward on voltage ISD = 60 A, VGS = 0 - 1.2 V trr Reverse recovery time - 72 ns Qrr Reverse recovery charge - 215 nC IRRM Reverse recovery current ISD = 120 A, VDD = 80 V di/dt = 100 A/μs, Tj = 150 °C (see Figure 15) - 6 A ISD 1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 μs, duty cycle 1.5% DocID026168 Rev 1 5/18 18 Electrical characteristics 2.1 STB120N10F4, STP120N10F4 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance $0Y ,' $ LV DĆ UH ĆD 6RQ V L ' ĆWK 5 ĆLQ D[Ć LRQ P DW ĆE\Ć U H G 2S LWH /LP   PV PV 7M ƒ& 7F ƒ&  PV 6LQOJH SXOVH     9'69 Figure 4. Output characteristics Figure 5. Transfer characteristics $0Y ,' $ 9*6 Ć9  $0Y ,' $ 9'6 9  9     9     9            9 9'69 Figure 6. Gate charge vs gate-source voltage $0Y 9*6 9 9'' 9   ,' $           9*69 Figure 7. Static drain-source on-resistance $0Y 5'6RQ P2KP 9*6 9              6/18          4JQ&   DocID026168 Rev 1       ,'$ STB120N10F4, STP120N10F4 Electrical characteristics Figure 8. Capacitance variations Figure 9. Source-drain diode forward characteristics $0Y & S)  AM15511v1 VSD (V) TJ=-50°C 1   &LVV 0.9   0.8  TJ=25°C 0.7   TJ=150°C 0.6        &RVV &UVV  9'69 Figure 10. Normalized gate threshold voltage vs temperature AM15508v1 VGS(th) (norm) ID=250 µA 0.5 0 1 2 0.8 1.5 0.6 1 0.4 0.5 25 75 125 60 80 100 ISD(A) AM15509v1 RDS(on) (norm) 2.5 -25 40 Figure 11. Normalized on-resistance vs temperature 1.2 0.2 -75 20 TJ(°C) 0 -75 VGS=10 V ID=60 A -25 25 75 125 TJ(°C) Figure 12. Normalized V(BR)DSS vs temperature AM15510v1 V(BR)DSS (norm) ID=250 µA 1.15 1.1 1.05 1 0.95 0.9 0.85 -75 -25 25 75 125 TJ(°C) DocID026168 Rev 1 7/18 18 Test circuits 3 STB120N10F4, STP120N10F4 Test circuits Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF IG=CONST VDD VGS 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times A A AM01469v1 Figure 16. Unclamped inductive load test circuit L A D G D.U.T. FAST DIODE B B VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 8/18 0 DocID026168 Rev 1 10% AM01473v1 STB120N10F4, STP120N10F4 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID026168 Rev 1 9/18 18 Package mechanical data 4.1 STB120N10F4, STP120N10F4 D2PAK, STB120N10F4 Figure 19. D²PAK (TO-263) drawing 0079457_T 10/18 DocID026168 Rev 1 STB120N10F4, STP120N10F4 Package mechanical data Table 8. D²PAK (TO-263) mechanical data mm Dim. Min. Typ. Max. A 4.40 4.60 A1 0.03 0.23 b 0.70 0.93 b2 1.14 1.70 c 0.45 0.60 c2 1.23 1.36 D 8.95 9.35 D1 7.50 E 10 E1 8.50 10.40 e 2.54 e1 4.88 5.28 H 15 15.85 J1 2.49 2.69 L 2.29 2.79 L1 1.27 1.40 L2 1.30 1.75 R V2 0.4 0° 8° DocID026168 Rev 1 11/18 18 Package mechanical data STB120N10F4, STP120N10F4 Figure 20. D²PAK footprint(a) 16.90 12.20 5.08 1.60 3.50 9.75 a. All dimension are in millimeters 12/18 DocID026168 Rev 1 Footprint STB120N10F4, STP120N10F4 4.2 Package mechanical data TO-220, STP120N10F4 Figure 21. TO-220 type A drawing BW\SH$B5HYB7 DocID026168 Rev 1 13/18 18 Package mechanical data STB120N10F4, STP120N10F4 Table 9. TO-220 type A mechanical data mm Dim. Min. Typ. A 4.40 4.60 b 0.61 0.88 b1 1.14 1.70 c 0.48 0.70 D 15.25 15.75 D1 14/18 Max. 1.27 E 10 10.40 e 2.40 2.70 e1 4.95 5.15 F 1.23 1.32 H1 6.20 6.60 J1 2.40 2.72 L 13 14 L1 3.50 3.93 L20 16.40 L30 28.90 ÆP 3.75 3.85 Q 2.65 2.95 DocID026168 Rev 1 STB120N10F4, STP120N10F4 5 Packaging mechanical data Packaging mechanical data Figure 22. Tape 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F K0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v2 DocID026168 Rev 1 15/18 18 Packaging mechanical data STB120N10F4, STP120N10F4 Figure 23. Reel T REEL DIMENSIONS 40mm min. Access hole At slot location B D C N A Full radius G measured at hub Tape slot in core for tape start 25 mm min. width AM08851v2 Table 10. D²PAK (TO-263) tape and reel mechanical data Tape Reel mm mm Dim. 16/18 Dim. Min. Max. A0 10.5 10.7 A B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 F 11.4 11.6 N 100 K0 4.8 5.0 T P0 3.9 4.1 P1 11.9 12.1 Base qty 1000 P2 1.9 2.1 Bulk qty 1000 R 50 T 0.25 0.35 W 23.7 24.3 DocID026168 Rev 1 Min. Max. 330 13.2 26.4 30.4 STB120N10F4, STP120N10F4 6 Revision history Revision history Table 11. Document revision history Date Revision 02-Apr-2014 1 Changes First release. DocID026168 Rev 1 17/18 18 STB120N10F4, STP120N10F4 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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