STB20N90K5

STB20N90K5 Datasheet N-channel 900 V, 0.21 Ω typ., 20 A MDmesh™ K5 Power MOSFET in a D²PAK package Features TAB 2 1 3 D²PAK Order code VDS RDS(on ) max. ID STB20N90K5 900 V 0.25 Ω 20 A • Industry’s lowest RDS(on) x area • • • • Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected D(2, TAB) Applications • G(1) Switching applications Description S(3) AM01475V1 This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Product status link STB20N90K5 Product summary Order code STB20N90K5 Marking 20N90K5 Package D²PAK Packing Tape and reel DS11568 - Rev 4 - October 2018 For further information contact your local STMicroelectronics sales office. www.st.com STB20N90K5 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Gate-source voltage ±30 V ID Drain current (continuous) at TC = 25 °C 20 A ID Drain current (continuous) at TC = 100 °C 13 A ID (1) Drain current (pulsed) 80 A PTOT Total dissipation at TC = 25 °C 250 W dv/dt (2) Peak diode recovery voltage slope 4.5 dv/dt (3) MOSFET dv/dt ruggedness 50 VGS Tj Parameter Operating junction temperature range Tstg V/ns -55 to 150 °C Value Unit Thermal resistance junction-case 0.5 °C/W Thermal resistance junction-pcb 30 °C/W Value Unit Storage temperature range 1. Pulse width limited by safe operating area. 2. ISD ≤ 20 A, di/dt ≤ 100 A/μs; VDS peak ≤ V(BR)DSS, VDD= 450 V. 3. VDS ≤ 720 V. Table 2. Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter 1. When mounted on a 1-inch² FR-4, 2 Oz copper board. Table 3. Avalanche characteristics Symbol DS11568 - Rev 4 Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 6.5 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 500 mJ page 2/15 STB20N90K5 Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified Table 4. On/off-state Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions VGS = 0 V, ID = 1 mA Min. Typ. 900 IDSS 1 µA 50 µA ±10 µA 4 5 V 0.21 0.25 Ω Min. Typ. Max. Unit - 1500 - pF - 120 - pF - 1 - pF - 78 - pF 220 - pF VGS = 0 V, VDS = 900 V TC = 125 °C (1) Gate body leakage current VDS = 0 V, VGS = ±20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 10 A IGSS Unit V VGS = 0 V, VDS = 900 V Zero gate voltage drain current Max. 3 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Ciss Coss Crss Parameter Test conditions Input capacitance Output capacitance Reverse transfer capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V Co(er) (1) Equivalent capacitance energy related Co(tr) (2) Equivalent capacitance time related Rg Intrinsic gate resistance f = 1 MHz , ID = 0 A - 3.7 - Ω Qg Total gate charge VDD = 720 V, ID = 20 A - 40 - nC Qgs Gate-source charge - 14 - nC Qgd Gate-drain charge VGS= 0 to 10 V (see Figure 14. Test circuit for gate charge behavior) - 17 - nC VGS = 0 V, VDS = 0 to 720 V 1. Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS. 2. Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. DS11568 - Rev 4 page 3/15 STB20N90K5 Electrical characteristics Table 6. Switching times Symbol td(on) tr td(off) tf Parameter Test conditions Min. Typ. Max. Unit Turn-on delay time VDD= 450 V, ID = 10 A, - 20.2 - ns Rise time RG = 4.7 Ω - 13.5 - ns Turn-off delay time VGS = 10 V (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) - 64.7 - ns - 16 - ns Min. Typ. Max. Unit Fall time Table 7. Source-drain diode Symbol Parameter Test conditions ISD Source-drain current - 20 A ISDM (1) Source-drain current (pulsed) - 80 A VSD (2) Forward on voltage ISD = 20 A, VGS = 0 V - 1.5 V trr Reverse recovery time ISD = 20 A, di/dt = 100 A/µs, - 517 ns Qrr Reverse recovery charge - 11.4 µC IRRM Reverse recovery current VDD = 60 V (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 44 A ISD = 20 A, di/dt = 100 A/µs, - 674 ns trr Reverse recovery time Qrr Reverse recovery charge VDD = 60 V, - 14 µC Reverse recovery current Tj = 150 °C (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 41.6 A Min. Typ. Max. Unit 30 - - V IRRM 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 8. Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS= ±1 mA, ID= 0 A The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry. DS11568 - Rev 4 page 4/15 STB20N90K5 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area ID (A) GIPG301120161112SOA 10 1 t p =10 µs t p =100 µs Operation in this area is limited by R DS(on) t p =1 ms t p =10 ms 10 0 10 -1 10 -1 Figure 2. Thermal impedance T j ≤150 °C T c = 25°C single pulse 10 0 10 1 10 2 V DS (V) Figure 3. Output characteristics ID (A) GIPG291120161015OCH V GS =10, 11 V 50 40 GIPG291120161014TCH V DS = 20 V 40 V GS =9 V 30 V GS =8 V 20 10 20 10 V GS =7 V V GS =6 V 4 8 12 16 V DS (V) Figure 5. Normalized V(BR)DSS vs temperature V (BR)DSS (norm.) 1.12 ID (A) 50 30 0 0 Figure 4. Transfer characteristics GIPG291120161015BDV 0 5 1.08 7 8 9 10 V GS (V) Figure 6. Static drain-source on-resistance R DS(on) (Ω) 0.23 I D = 1 mA 6 GIPG291120161014RID V GS =10 V 0.22 1.04 0.21 1.00 0.20 0.96 0.19 0.92 0.88 -50 DS11568 - Rev 4 0 50 100 T j (°C) 0.18 0 5 10 15 I D (A) page 5/15 STB20N90K5 Electrical characteristics (curves) Figure 7. Gate charge vs gate-source voltage V GS (V) GIPG291120161013QVG V DS (V) V DS 14 600 10 500 8 400 6 300 4 200 2 100 0 0 10 20 30 40 0 Q g (nC) Figure 9. Normalized gate threshold voltage vs temperature V GS(th) (norm.) GIPG291120161016VTH GIPG291120161011CVR 10 4 C ISS 10 3 10 2 C OSS f = 1 MHz 10 1 C RSS 10 0 10 -1 10 0 10 1 10 2 V DS (V) Figure 10. Normalized on-resistance vs temperature R DS(on) (norm.) GIPG291120161017RON 2.6 I D = 100 µA 1.2 C (pF) 700 V DD = 720 V I D = 20 A 12 Figure 8. Capacitance variation V GS = 10 V 2.2 1.0 1.8 0.8 1.4 0.6 1.0 0.4 0.6 0.2 -50 0 50 100 T j (°C) Figure 11. Maximum avalanche energy vs. starting TJ E AS (mJ) GIPG291120161018EAS 0.2 -50 0 50 100 T j (°C) Figure 12. Source-drain diode forward characteristics VSD (V) GIPD280920181027SDF 1.1 500 Single pulse I D = 6.5 A V DD = 50 V 400 300 1 0.8 0.7 200 Tj = -50 °C 0.9 Tj = 25 °C Tj = 150 °C 0.6 100 0 -50 -25 DS11568 - Rev 4 0.5 0 25 50 75 100 125 T J (°C) 0.4 5 10 15 ISD (A) page 6/15 STB20N90K5 Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD RL RL 2200 + μF 3.3 μF VDD VD RG VGS IG= CONST VGS + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v10 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A VD 100 µH fast diode B B B 3.3 µF D G + Figure 16. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) toff td(off) tr tf VD 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS11568 - Rev 4 page 7/15 STB20N90K5 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS11568 - Rev 4 page 8/15 STB20N90K5 D²PAK (TO-263) type A2 package information 4.1 D²PAK (TO-263) type A2 package information Figure 19. D²PAK (TO-263) type A2 package outline 0079457_A2_25 DS11568 - Rev 4 page 9/15 STB20N90K5 D²PAK (TO-263) type A2 package information Table 9. D²PAK (TO-263) type A2 package mechanical data Dim. mm Min. Typ. Max. A 4.40 4.60 A1 0.03 0.23 b 0.70 0.93 b2 1.14 1.70 c 0.45 0.60 c2 1.23 1.36 D 8.95 9.35 D1 7.50 7.75 8.00 D2 1.10 1.30 1.50 E 10.00 E1 8.70 8.90 9.10 E2 7.30 7.50 7.70 e 10.40 2.54 e1 4.88 5.28 H 15.00 15.85 J1 2.49 2.69 L 2.29 2.79 L1 1.27 1.40 L2 1.30 1.75 R V2 0.40 0° 8° Figure 20. D²PAK (TO-263) recommended footprint (dimensions are in mm) Footprint DS11568 - Rev 4 page 10/15 STB20N90K5 D²PAK packing information 4.2 D²PAK packing information Figure 21. D²PAK tape outline DS11568 - Rev 4 page 11/15 STB20N90K5 D²PAK packing information Figure 22. D²PAK reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 10. D²PAK tape and reel mechanical data Tape Dim. DS11568 - Rev 4 Reel mm mm Dim. Min. Max. Min. A0 10.5 10.7 A B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 F 11.4 11.6 N 100 K0 4.8 5.0 T Max. 330 13.2 26.4 30.4 P0 3.9 4.1 P1 11.9 12.1 Base quantity 1000 P2 1.9 2.1 Bulk quantity 1000 R 50 T 0.25 0.35 W 23.7 24.3 page 12/15 STB20N90K5 Revision history Table 11. Document revision history Date Revision 19-May-2016 1 Changes First release. Modified title and RDS(on) in features table Modified Table 4: "Avalanche characteristics", Table 5: "On/off-state", Table 6: "Dynamic", Table 7: "Switching times", Table 8: "Source-drain diode" 01-Dec-2016 2 Added Section 2.1: "Electrical characteristics (curves)" Modified Section 3: "Test circuits" Datasheet promoted from preliminary data to production data Minor text changes 24-Jan-2017 3 04-Oct-2018 4 Modified Table 7: "Switching times". Minor text changes. Removed maturity status indication from cover page. Added Figure 12. Source-drain diode forward characteristics. Minor text changes. DS11568 - Rev 4 page 13/15 STB20N90K5 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 D²PAK (TO-263) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 D²PAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DS11568 - Rev 4 page 14/15 STB20N90K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS11568 - Rev 4 page 15/15