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STB25NF06LAG

STB25NF06LAG

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

    SOT404

  • 描述:

    MOSFETN-CH60V25AD2PAK

  • 详情介绍
  • 数据手册
  • 价格&库存
STB25NF06LAG 数据手册
STB25NF06LAG Automotive-grade N-channel 60 V, 53 mΩ typ., 20 A STripFET™ II Power MOSFET in a D²PAK package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STB25NF06LAG 60 V 70 mΩ 20 A 60 W TAB     2 3 1 AEC-Q101 qualified Exceptional dv/dt capability 100% avalanche tested Low gate charge D²PAK Applications  Switching applications Figure 1: Internal schematic diagram Description This Power MOSFET series realized with STMicroelectronics unique STripFET™ process is specifically designed to minimize input capacitance and gate charge. It is therefore ideal as a primary switch in advanced high-efficiency isolated DC-DC converters for Telecom and Computer applications. It is also suitable for any application with low gate charge drive requirements. D(2, TAB) G(1) S(3) AM01475v1_Tab Table 1: Device summary Order code Marking Package Packing STB25NF06LAG 25NF06L D²PAK Tape and reel November 2016 DocID030043 Rev 1 This is information on a product in full production. 1/15 www.st.com Contents STB25NF06LAG Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/15 4.1 D²PAK package information .............................................................. 9 4.2 D²PAK packing information ............................................................. 12 Revision history ............................................................................ 14 DocID030043 Rev 1 STB25NF06LAG 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 60 V VGS Gate-source voltage ±18 V Drain current (continuous) at Tcase = 25 °C 20 Drain current (continuous) at Tcase = 100 °C 14 IDM(1) Drain current (pulsed) 77 A PTOT Total dissipation at Tcase = 25 °C 60 W EAS(2) Single pulse avalanche energy 180 mJ -55 to 175 °C ID Tstg Tj Storage temperature range Operating junction temperature range A Notes: (1) Pulse width is limited by safe operating area. (2) starting Tj = 25 °C, ID = 10 A, VDD = 40 V. Table 3: Thermal data Symbol Parameter Value Rthj-case Thermal resistance junction-case 2.5 Rthj-pcb(1) Thermal resistance junction-pcb 35 Unit °C/W Notes: (1) When mounted on a 1-inch² FR-4, 2 Oz copper board. DocID030043 Rev 1 3/15 Electrical characteristics 2 STB25NF06LAG Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 4: Static Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 250 µA Min. Typ. 60 IDSS Unit V VGS = 0 V, VDS = 60 V Zero gate voltage drain current Max. 1 µA VGS = 0 V, VDS = 60 V, Tcase = 125 °C(1) 100 Gate-body leakage current VDS = 0 V, VGS = ±18 V ±100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2.5 V RDS(on) Static drain-source on-resistance IGSS 1 VGS = 10 V, ID = 10 A 53 VGS = 5 V, ID = 10 A 62 85 Min. Typ. Max. - 370 - - 102 - - 44 - - 13 - - 2 - - 5 - 70 mΩ Notes: (1)Defined by design, not subject to production test. Table 5: Dynamic Symbol 4/15 Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS = 25 V, f = 1 MHz, VGS = 0 V VDD = 30 V, ID = 20 A, VGS = 10 V (see Figure 14: "Test circuit for gate charge behavior") DocID030043 Rev 1 Unit pF nC STB25NF06LAG Electrical characteristics Table 6: Switching times Symbol td(on) tr td(off) tf Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. VDD = 30 V, ID = 10 A, RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform") - 7 - - 11 - - 22 - Unit ns - 5 - Min. Typ. Max. Unit Table 7: Source-drain diode Symbol Parameter Test conditions ISD Source-drain current - 20 A ISDM(1) Source-drain current (pulsed) - 77 A VSD(2) Forward on voltage - 1.2 V VGS = 0 V, ISD = 20 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 20 A, di/dt = 100 A/µs, VDD = 48 V (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 49 ns - 61 nC - 2.5 A Notes: (1) Pulse width limited by safe operating area . (2) Pulse test: pulse duration = 300 µs, duty cycle 1.5 %. DocID030043 Rev 1 5/15 Electrical characteristics 2.1 STB25NF06LAG Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 5: Transfer characteristics Figure 4: Output characteristics Figure 6: Gate charge vs gate-source voltage 6/15 Figure 7: Static drain-source on-resistance DocID030043 Rev 1 STB25NF06LAG Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Source-drain diode forward characteristics DocID030043 Rev 1 7/15 Test circuits 3 STB25NF06LAG Test circuits Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform 8/15 DocID030043 Rev 1 Figure 18: Switching time waveform STB25NF06LAG 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 D²PAK package information Figure 19: D²PAK (TO-263) type A package outline 0079457_A_rev22 DocID030043 Rev 1 9/15 Package information STB25NF06LAG Table 8: D²PAK (TO-263) type A package mechanical data mm Dim. Min. Max. A 4.40 4.60 A1 0.03 0.23 b 0.70 0.93 b2 1.14 1.70 c 0.45 0.60 c2 1.23 1.36 D 8.95 9.35 D1 7.50 7.75 8.00 D2 1.10 1.30 1.50 E 10 E1 8.50 8.70 8.90 E2 6.85 7.05 7.25 e 10.40 2.54 e1 4.88 5.28 H 15 15.85 J1 2.49 2.69 L 2.29 2.79 L1 1.27 1.40 L2 1.30 1.75 R V2 10/15 Typ. 0.4 0° DocID030043 Rev 1 8° STB25NF06LAG Package information Figure 20: D²PAK (TO-263) recommended footprint (dimensions are in mm) DocID030043 Rev 1 11/15 Package information 4.2 STB25NF06LAG D²PAK packing information Figure 21: Tape outline 12/15 DocID030043 Rev 1 STB25NF06LAG Package information Figure 22: Reel outline Table 9: D²PAK tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 10.5 10.7 A B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 F 11.4 11.6 N 100 K0 4.8 5.0 T P0 3.9 4.1 P1 11.9 12.1 Base quantity 1000 P2 1.9 2.1 Bulk quantity 1000 R 50 T 0.25 0.35 W 23.7 24.3 DocID030043 Rev 1 Min. Max. 330 13.2 26.4 30.4 13/15 Revision history 5 STB25NF06LAG Revision history Table 10: Document revision history 14/15 Date Revision 24-Nov-2016 1 DocID030043 Rev 1 Changes First release. STB25NF06LAG IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID030043 Rev 1 15/15
STB25NF06LAG
物料型号: - 型号:STB25NF06LAG

器件简介: - 这是一个汽车级N沟道60V,典型值为53mΩ,20A的STripFET™ II功率MOSFET,使用D²PAK封装。 - 该系列MOSFET采用STMicroelectronics独特的STripFET™工艺,专为最小化输入电容和栅极电荷而设计,非常适合作为电信和计算机应用中的高效隔离式DC-DC转换器的主开关。

引脚分配: - D(2, TAB):漏极 - G(1):栅极 - S(3):源极

参数特性: - 绝对最大额定值包括60V的漏源电压,±18V的栅源电压,25°C时连续漏电流20A,100°C时14A,脉冲漏电流77A,总功耗60W,单脉冲雪崩能量180mJ,存储温度范围-55至175℃,工作结温范围未具体说明。 - 热数据包括结到外壳的热阻2.5°C/W,结到PCB的热阻35°C/W(在1平方英寸FR-4,2盎司铜板上)。

功能详解: - 电气特性包括静态和动态参数,如漏源击穿电压、零栅极电压下的漏电流、栅体漏电流、栅极阈值电压、静态漏源导通电阻、输入电容、输出电容、反向传输电容、总栅极电荷等。 - 开关时间包括开通延迟时间、上升时间、关断延迟时间和下降时间。 - 源-漏二极管特性,包括正向导通电压、反向恢复时间、反向恢复电荷、反向恢复电流等。

应用信息: - 主要应用于开关应用,特别是在需要低栅极电荷驱动的场合。

封装信息: - 提供了D²PAK封装的详细信息,包括机械尺寸、推荐的焊盘尺寸以及卷带封装信息
STB25NF06LAG 价格&库存

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STB25NF06LAG
  •  国内价格 香港价格
  • 1+11.083391+1.38429
  • 10+9.1011310+1.13671
  • 100+7.07749100+0.88396
  • 500+5.99914500+0.74928

库存:1578

STB25NF06LAG
  •  国内价格 香港价格
  • 1000+4.887001000+0.61038
  • 2000+4.600532000+0.57460
  • 5000+4.381445000+0.54723
  • 10000+4.1792210000+0.52198

库存:1578