STB41N40DM6AG

STB41N40DM6AG Datasheet Automotive-grade N-channel 400 V, 0.050 Ω typ., 41 A, MDmesh™ DM6 Power MOSFET in a D²PAK package Features TAB 2 Order code VDS RDS(on) max. ID STB41N40DM6AG 400 V 0.065 Ω 41 A 3 1 D²PAK D(2, TAB) • • • AEC-Q101 qualified Fast-recovery body diode Lower RDS(on) per area vs previous generation • • • • Low gate charge, input capacitance and resistance 100% avalanche tested Extremely high dv/dt ruggedness Zener-protected Applications G(1) • Switching applications Description S(3) NG1D2TS3Z Product status link STB41N40DM6AG This high-voltage N-channel Power MOSFET is part of the MDmesh™ DM6 fastrecovery diode series. Compared with the previous MDmesh fast generation, DM6 combines very low recovery charge (Qrr), recovery time (trr) and excellent improvement in RDS(on) per area with one of the most effective switching behaviors available in the market for the most demanding high-efficiency bridge topologies and ZVS phase-shift converters. Product summary Order code STB41N40DM6AG Marking 41N40DM6 Package D2PAK Packing Tape and reel DS12571 - Rev 1 - May 2018 For further information contact your local STMicroelectronics sales office. www.st.com STB41N40DM6AG Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Gate-source voltage ±25 V Drain current (continuous) at TC = 25 °C 41 A Drain current (continuous) at TC = 100 °C 26 A IDM(1) Drain current (pulsed) 150 A PTOT Total dissipation at TC = 25 °C 250 W dv/dt(2) Peak diode recovery voltage slope 50 dv/dt(3) MOSFET dv/dt ruggedness 100 VGS ID TJ Parameter Operating junction temperature range Tstg Storage temperature range V/ns -55 to 150 °C Value Unit 1. Pulse width limited by safe operating area 2. ISD ≤ 41 A, di/dt ≤ 800 A/μs, VDS peak < V(BR)DSS, VDD = 320 V 3. VDS ≤ 320 V Table 2. Thermal data Symbol Rthj-case (1) Rthj-pcb Parameter Thermal resistance junction-case 0.5 Thermal resistance junction-pcb 30 °C/W 1. When mounted on an 1-inch² FR-4, 2 Oz copper board. Table 3. Avalanche characteristics Symbol IAR EAS DS12571 - Rev 1 Parameter Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) Single pulse avalanche energy (starting Tj = 25°C, ID = IAR, VDD = 100 V) Value Unit 6 A 760 mJ page 2/14 STB41N40DM6AG Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified Table 4. On-/off-states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS= 0 V, ID = 1 mA Min. Typ. 400 Zero gate voltage drain current 1 µA 100 µA ±1 µA 4 5 V 0.050 0.065 Ω Min. Typ. Max. Unit - 2310 - pF - 151 - pF - 10 - pF VGS = 0 V, VDS = 400 V, TC = 125 °C(1) IGSS Gate body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 20.5 A Unit V VGS = 0 V, VDS = 400 V IDSS Max. 3 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 320 V, VGS = 0 V - 450 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 1.3 - Ω Qg Total gate charge VDD = 320 V, ID = 41 A, - 53 - nC Qgs Gate-source charge VGS = 0 to 10 V - 12 - nC Qgd Gate-drain charge (see Figure 14. Test circuit for gate charge behavior) - 29 - nC VDS = 100 V, f = 1 MHz, VGS = 0 V 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS12571 - Rev 1 Parameter Test conditions Min. Typ. Max. Unit Turn-on delay time VDD = 200 V, ID = 20.5 A, - 18 - ns Rise time RG = 4.7 Ω, VGS = 10 V - 10.3 - ns Turn-off delay time (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) - 46 - ns - 9.4 - ns Fall time page 3/14 STB41N40DM6AG Electrical characteristics Table 7. Source-drain diode Symbol ISD ISDM(1) (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 41 A Source-drain current (pulsed) - 150 A 1.6 V Forward on voltage ISD = 41 A, VGS = 0 V - trr Reverse recovery time ISD = 41 A, di/dt = 100 A/µs, - 103 ns Qrr Reverse recovery charge VDD = 60 V - 0.44 µC Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 8.5 A trr Reverse recovery time ISD = 41 A, di/dt = 100 A/µs, - 180 ns Qrr Reverse recovery charge VDD = 60 V, Tj = 150 °C - 1.5 µC IRRM Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 17 A Min. Typ. Max. Unit ±30 - - V VSD IRRM 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 8. Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS = ±1 mA, ID = 0 A The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DS12571 - Rev 1 page 4/14 STB41N40DM6AG Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area ID (A) 10 2 Figure 2. Thermal impedance GADG020520181249SOA Operation in this area is limited by RDS(on) tp =10 µs 10 1 tp =100 µs Single pulse, TC = 25 °C, TJ ≤ 150 °C, VGS = 10 V 10 0 tp =1 ms tp =10 ms 10 -1 10 -1 10 10 0 10 1 VDS (V) 2 Figure 3. Output characteristics ID (A) Figure 4. Transfer characteristics ID (A) GADG020520181250OCH VGS = 10 V 140 GADG020520181250TCH 140 VGS = 9 V 120 120 VGS = 8 V 100 VGS = 7 V 80 80 60 60 40 40 VGS = 6 V 20 0 0 20 VGS = 5 V 2 4 6 8 10 12 14 VDS (V) Figure 5. Gate charge vs gate-source voltage VGS (V) GADG020520181251QVG VDS (V) VDS 12 0 4 250 54 200 52 6 150 50 4 100 48 2 50 46 VDD = 320 V ID = 41 A 8 DS12571 - Rev 1 10 20 30 40 6 7 RDS(on) (mΩ) 56 10 5 8 9 VGS (V) Figure 6. Static drain-source on-resistance 300 0 0 VDS = 16 V 100 GADG020520181252RID VGS = 10 V 50 60 0 Qg (nC) 44 0 8 16 24 32 40 ID (A) page 5/14 STB41N40DM6AG Electrical characteristics (curves) Figure 8. Normalized gate threshold voltage vs temperature Figure 7. Capacitance variations C (pF) GADG020520181252CVR VGS(th) (norm.) 104 GADG020520181253VTH 1.1 CISS 103 102 COSS 101 CRSS 1 0.9 ID = 250 µA 0.8 0.7 100 10-1 100 101 102 VDS (V) Figure 9. Normalized on-resistance vs temperature RDS(on) (norm.) GADG020520181253RON 2.5 0.6 -75 25 75 125 Tj (°C) Figure 10. Normalized VBR(DSS) vs temperature V(BR)DSS (norm.) GADG020520181253BDV 1.1 2 1 1 0.95 0.5 0.9 -25 25 75 125 Tj (°C) Figure 11. Source-drain diode forward characteristics VSD (V) ID = 1 mA 1.05 VGS = 10 V ID = 20 A 1.5 0 -75 -25 GADG020520181254SDF TJ = -55 °C 0.85 -75 -25 25 75 125 Tj (°C) Figure 12. Output capacitance stored energy EOSS (µJ) GADG020520181254EOS 12 1 TJ = 25 °C 10 0.8 8 TJ = 150 °C 6 0.6 4 0.4 0.2 0 DS12571 - Rev 1 2 8 16 24 32 40 ISD (A) 0 0 80 160 240 320 400 VDS (V) page 6/14 STB41N40DM6AG Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 16. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform V(BR)DSS ton VD td(on) 90% IDM tf 90% 10% 10% 0 ID VDD toff td(off) tr VDD VGS 0 VDS 90% 10% AM01472v1 AM01473v1 DS12571 - Rev 1 page 7/14 STB41N40DM6AG Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 D²PAK (TO-263) type A2 package information Figure 19. D²PAK (TO-263) type A2 package outline 0079457_A2_24 DS12571 - Rev 1 page 8/14 STB41N40DM6AG D²PAK (TO-263) type A2 package information Table 9. D²PAK (TO-263) type A2 package mechanical data Dim. mm Min. Typ. Max. A 4.40 4.60 A1 0.03 0.23 b 0.70 0.93 b2 1.14 1.70 c 0.45 0.60 c2 1.23 1.36 D 8.95 9.35 D1 7.50 7.75 8.00 D2 1.10 1.30 1.50 E 10.00 E1 8.70 8.90 9.10 E2 7.30 7.50 7.70 e 10.40 2.54 e1 4.88 5.28 H 15.00 15.85 J1 2.49 2.69 L 2.29 2.79 L1 1.27 1.40 L2 1.30 1.75 R V2 0.40 0° 8° Figure 20. D²PAK (TO-263) recommended footprint (dimensions are in mm) Footprint DS12571 - Rev 1 page 9/14 STB41N40DM6AG D²PAK packing information 4.2 D²PAK packing information Figure 21. D²PAK tape outline DS12571 - Rev 1 page 10/14 STB41N40DM6AG D²PAK packing information Figure 22. D²PAK reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 10. D²PAK tape and reel mechanical data Tape Dim. DS12571 - Rev 1 Reel mm mm Dim. Min. Max. Min. A0 10.5 10.7 A B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 F 11.4 11.6 N 100 K0 4.8 5.0 T Max. 330 13.2 26.4 30.4 P0 3.9 4.1 P1 11.9 12.1 Base quantity 1000 P2 1.9 2.1 Bulk quantity 1000 R 50 T 0.25 0.35 W 23.7 24.3 page 11/14 STB41N40DM6AG Revision history Table 11. Document revision history DS12571 - Rev 1 Date Version 17-May-2018 1 Changes Initial release. The document status is production data. page 12/14 STB41N40DM6AG Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 D²PAK (TO-263) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 D²PAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 DS12571 - Rev 1 page 13/14 STB41N40DM6AG IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS12571 - Rev 1 page 14/14