STB43N65M5

STB43N65M5 Datasheet Automotive-grade N-channel 650 V, 0.058 Ω typ., 42 A MDmesh™ M5 Power MOSFET in a D²PAK package Features TAB 2 Order code VDS RDS(on) max. ID PTOT STB43N65M5 650 V 0.063 Ω 42 A 250 W 3 1 D²PAK D(2, TAB) • • AEC-Q101 qualified Extremely low RDS(on) • • • Low gate charge and input capacitance Excellent switching performance 100% avalanche tested Applications • G(1) Switching applications Description S(3) AM01475v1_noZen This device is an N-channel Power MOSFET based on the MDmesh™ M5 innovative vertical process technology combined with the well-known PowerMESH™ horizontal layout. The resulting product offers extremely low on-resistance, making it particularly suitable for applications requiring high power and superior efficiency. Product status link STB43N65M5 Product summary Order code STB43N65M5 Marking 43N65M5 Package D²PAK Packing Tape and reel DS11173 - Rev 2 - November 2018 For further information contact your local STMicroelectronics sales office. www.st.com STB43N65M5 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit Gate-source voltage ±25 V Drain current (continuous) at Tcase = 25 °C 42 Drain current (continuous) at Tcase = 100 °C 26.5 IDM (1) Drain current (pulsed) 168 A PTOT Total power dissipation at Tcase = 25 °C 250 W dv/dt(2) Peak diode recovery voltage slope 15 dv/dt(3) MOSFET dv/dt ruggedness 50 Tstg Storage temperature range VGS ID Tj Operating junction temperature range A V/ns -55 to 150 °C 1. Pulse width is limited by safe operating area. 2. ISD ≤ 42 A, di/dt=150 A/μs; VDS peak < V(BR)DSS, VDD = 80% V(BR)DSS. 3. VDS ≤ 520 V. Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 0.5 Thermal resistance junction-pcb 30 Rthj-pcb (1) Value Unit °C/W 1. When mounted on a 1-inch² FR-4, 2 Oz copper board. Table 3. Avalanche characteristics Symbol IAR (1) EAS (2) Parameter Avalanche current, repetitive or not repetitive Single pulse avalanche energy Value Unit 7 A 650 mJ 1. (pulse width limited by Tjmax). 2. starting Tj = 25 °C, ID = IAR, VDD = 50 V. DS11173 - Rev 2 page 2/16 STB43N65M5 Electrical characteristics 2 Electrical characteristics (Tcase = 25 °C unless otherwise specified). Table 4. Static Symbol Parameter Test conditions Min. V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA 650 Typ. Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 21 A VGS = 0 V, VDS = 650 V, Tcase = 125 Unit V VGS = 0 V, VDS = 650 V IDSS Max. 1 °C(1) 100 µA ±100 nA 4 5 V 0.058 0.063 Ω Min. Typ. Max. Unit - 4400 - - 100 - Reverse transfer capacitance - 5.3 - Equivalent output capacitance VDS = 0 to 520 V, VGS = 0 V - 300 - pF - 1.2 - Ω - 100 - - 23 - - 40 - 3 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Coss eq. (1) RG Intrinsic gate resistance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V f = 1 MHz, ID = 0 A VDD = 520 V, ID = 21 A, VGS = 0 to 10 V (see Figure 15. Test circuit for gate charge behavior) pF nC 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS11173 - Rev 2 Parameter Test conditions Turn-on delay time Rise time Turn-off delay time Fall time VDD = 400 V, ID = 28 A RG = 4.7 Ω, VGS = 10 V (see Figure 14. Test circuit for resistive load switching times and Figure 19. Switching time waveform) Min. Typ. Max. - 73 - - 15 - - 12 - - 19 - Unit ns page 3/16 STB43N65M5 Electrical characteristics Table 7. Source-drain diode Symbol ISD ISDM (1) VSD (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 42 A Source-drain current (pulsed) - 168 A - 1.6 V Forward on voltage trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current VGS = 0 V, ISD = 42 A ISD = 42 A, di/dt = 100 A/µs, VDD = 100 V (see Figure 16. Test circuit for inductive load switching and diode recovery times) ISD = 42 A, di/dt = 100 A/µs, VDD = 100 V, Tj = 150 °C (see Figure 16. Test circuit for inductive load switching and diode recovery times) - 420 ns - 8 µC - 40 A - 530 ns - 12 µC - 44 A 1. Pulse width is limited by safe operating area. 2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DS11173 - Rev 2 page 4/16 STB43N65M5 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance GIPG230715M5FLA1BSOA ID (A) ) S( on 10 μs 100 μs 1 ms D O lim per ite ati d on by in m th ax is . R ar e a is 10 2 10 1 10 0 10 -1 10 -1 10 0 10 ms T j = 150 °C T c = 25 °C single pulse 10 1 10 2 V DS (V) Figure 3. Output characteristics ID (A) ID (A) GIPG220715M5FLA1BOCH V GS = 9,10 V V GS = 8 V 100 80 Figure 4. Transfer characteristics 80 60 60 40 40 20 20 4 8 V GS = 6 V 16 V DS (V) 12 Figure 5. Gate charge vs gate-source voltage GIPG230715M5FLA1BQVG VGS (V) 10 V DD = 520V I D = 21 A VDS V DS = 25V 100 V GS = 7 V 0 0 GIPG220715M5FLA1BTCH 0 3 R DS(on) (Ω) 500 0.062 400 6 300 4 200 2 100 5 6 7 8 9 V GS (V) Figure 6. Static drain-source on-resistance VDS (V) 8 4 GIPG230715M5FLA1BRID V GS = 10 V 0.060 0.058 0.056 0 0 DS11173 - Rev 2 20 40 60 80 0 100 Q g (nC) 0.054 0.052 0.050 0 10 20 30 40 I D (A) page 5/16 STB43N65M5 Electrical characteristics (curves) Figure 7. Capacitance variations GIPG220715M5FLA1BCVR Figure 8. Normalized gate threshold voltage vs temperature VGS(th) (norm.) 1.1 GIPG230715M5FLA1BVTH ID = 250 µA 1.0 0.9 0.8 0.7 -50 Figure 9. Normalized on-resistance vs temperature R DS(on) (norm.) GIPG230715M5FLA1BRON V GS = 10 V 2.1 0 50 T j (°C) 100 Figure 10. Normalized V(BR)DSS vs temperature V(BR)DSS (norm.) 1.08 GIPG230715M5FLA1BBDV ID = 1 mA 1.04 1.7 1.3 1.00 0.9 0.96 0.5 -50 0 50 100 T j (°C) Figure 11. Output capacitance stored energy E OSS (µJ) GIPG230715M5FLA1BEOS 0.92 -50 0 50 T j (°C) 100 Figure 12. Source- drain diode forward characteristics V SD (V) GIPG220715M5FLA1BSDF T j = -50 °C 1.2 16 T j = 25 °C 1.0 12 T j = 150 °C 0.8 0.6 8 0.4 4 0 0 DS11173 - Rev 2 0.2 100 200 300 400 500 600 V DS (V) 0 0 10 20 30 40 50 I SD (A) page 6/16 STB43N65M5 Electrical characteristics (curves) Figure 13. Switching energy vs gate resistance (Eon including reverse recovery of a SiC diode) E (μJ) 800 GIPG230715M5FLA1BSLR E ON V DD = 400 V V GS = 10 V I D = 28 A 600 400 E OFF 200 0 0 DS11173 - Rev 2 10 20 30 40 R G (Ω) page 7/16 STB43N65M5 Test circuits 3 Test circuits Figure 14. Test circuit for resistive load switching times Figure 15. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 16. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A B L A B 3.3 µF D G + VD 100 µH fast diode B Figure 17. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 18. Unclamped inductive waveform V(BR)DSS Figure 19. Switching time waveform Concept waveform for Inductive Load Turn-off Id VD 90%Vds 90%Id Tdelay -off IDM Vgs 90%Vgs on ID Vgs(I(t )) VDD VDD 10%Vds 10%Id Vds Trise AM01472v1 DS11173 - Rev 2 Tfall Tcross --over AM05540v2 page 8/16 STB43N65M5 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS11173 - Rev 2 page 9/16 STB43N65M5 D²PAK (TO-263) type A2 package information 4.1 D²PAK (TO-263) type A2 package information Figure 20. D²PAK (TO-263) type A2 package outline 0079457_A2_25 DS11173 - Rev 2 page 10/16 STB43N65M5 D²PAK (TO-263) type A2 package information Table 8. D²PAK (TO-263) type A2 package mechanical data Dim. mm Min. Typ. Max. A 4.40 4.60 A1 0.03 0.23 b 0.70 0.93 b2 1.14 1.70 c 0.45 0.60 c2 1.23 1.36 D 8.95 9.35 D1 7.50 7.75 8.00 D2 1.10 1.30 1.50 E 10.00 E1 8.70 8.90 9.10 E2 7.30 7.50 7.70 e 10.40 2.54 e1 4.88 5.28 H 15.00 15.85 J1 2.49 2.69 L 2.29 2.79 L1 1.27 1.40 L2 1.30 1.75 R V2 0.40 0° 8° Figure 21. D²PAK (TO-263) recommended footprint (dimensions are in mm) Footprint DS11173 - Rev 2 page 11/16 STB43N65M5 D²PAK packing information 4.2 D²PAK packing information Figure 22. D²PAK tape outline DS11173 - Rev 2 page 12/16 STB43N65M5 D²PAK packing information Figure 23. D²PAK reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 9. D²PAK tape and reel mechanical data Tape Dim. DS11173 - Rev 2 Reel mm mm Dim. Min. Max. Min. A0 10.5 10.7 A B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 F 11.4 11.6 N 100 K0 4.8 5.0 T Max. 330 13.2 26.4 30.4 P0 3.9 4.1 P1 11.9 12.1 Base quantity 1000 P2 1.9 2.1 Bulk quantity 1000 R 50 T 0.25 0.35 W 23.7 24.3 page 13/16 STB43N65M5 Revision history Table 10. Document revision history Date 23-Jul-2015 Revision Changes 1 Initial release. Updated features in cover page. 13-Nov-2018 2 Updated Section 3 Test circuits and Section 4.1 D²PAK (TO-263) type A2 package information. Minor text changes. DS11173 - Rev 2 page 14/16 STB43N65M5 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.1 D²PAK (TO-263) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 D²PAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 DS11173 - Rev 2 page 15/16 STB43N65M5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS11173 - Rev 2 page 16/16