STB45N40DM2AG

STB45N40DM2AG Datasheet Automotive-grade N-channel 400 V, 0.063 Ω typ., 38 A, MDmesh™ DM2 Power MOSFET in a D2PAK package Features TAB 2 Order code VDS RDS(on) max. ID PTOT STB45N40DM2AG 400 V 0.072 Ω 38 A 250 W 3 1 • • • • • • • D²PAK D(2, TAB) AEC-Q101 qualified Fast-recovery body diode Extremely low gate charge and input capacitance Low on-resistance 100% avalanche tested Extremely high dv/dt ruggedness Zener-protected G(1) Applications • S(3) Switching applications AM01475V1 Description This high-voltage N-channel Power MOSFET is part of the MDmesh™ DM2 fastrecovery diode series. It offers very low recovery charge (Qrr) and time (trr) combined with low RDS(on), rendering it suitable for the most demanding high-efficiency converters and ideal for bridge topologies and ZVS phase-shift converters. Product status STB45N40DM2AG Product summary Order code STB45N40DM2AG Marking 45N40DM2 Package D2PAK Packing Tape and reel DS11238 - Rev 4 - October 2018 For further information contact your local STMicroelectronics sales office. www.st.com STB45N40DM2AG Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Gate-source voltage ±25 V Drain current (continuous) at Tcase = 25 °C 38 Drain current (continuous) at Tcase = 100 °C 24 IDM(1) Drain current (pulsed) 110 A PTOT Total power dissipation at Tcase = 25 °C 250 W dv/dt(2) Peak diode recovery voltage slope 50 dv/dt(3) MOSFET dv/dt ruggedness 50 Tstg Storage temperature range VGS ID Tj Parameter Operating junction temperature range A V/ns -55 to 150 °C Value Unit 1. Pulse width is limited by safe operating area. 2. ISD ≤ 38 A, di/dt = 800 A/μs, VDS peak < V(BR)DSS,VDD = 80% V(BR)DSS 3. VDS ≤ 320 V Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 0.5 Thermal resistance junction-pcb 30 (1) Rthj-pcb °C/W 1. When mounted on an 1-inch² FR-4, 2 Oz copper board. Table 3. Avalanche characteristics Symbol IAR(1) (2) EAS Parameter Avalanche current, repetitive or not repetitive Single pulse avalanche energy Value Unit 7 A 1100 mJ 1. Pulse width is limited by Tjmax. 2. starting Tj = 25 °C, ID = IAR, VDD = 50 V DS11238 - Rev 4 page 2/15 STB45N40DM2AG Electrical characteristics 2 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 4. Static Symbol Parameter Test conditions Min. V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA 400 Typ. Max. Unit V VGS = 0 V, VDS = 400 V 10 VGS = 0 V, VDS = 400 V, Tcase = 125 °C(1) 100 ±5 µA 4 5 V 0.063 0.072 Ω Min. Typ. Max. Unit - 2600 - - 180 - IDSS Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 19 A 3 µA 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Ciss Parameter Test conditions Input capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance - 3.5 - Equivalent output capacitance VDS = 0 to 320 V, VGS = 0 V - 300 - pF Ω Coss eq.(1) RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 4 - Qg Total gate charge - 56 - Qgs Gate-source charge VDD = 320 V, ID = 38 A, VGS = 0 to 10 V - 13 - Qgd Gate-drain charge - 28 - (see Figure 14. Test circuit for gate charge behavior) pF nC 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS11238 - Rev 4 Parameter Test conditions Turn-on delay time VDD = 200 V, ID = 19 A, RG = 4.7 Ω, VGS = 10 V Rise time Turn-off delay time Fall time (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) Min. Typ. Max. - 20 - - 6.7 - - 68 - - 9.8 - Unit ns page 3/15 STB45N40DM2AG Electrical characteristics Table 7. Source-drain diode Symbol ISD ISDM(1) (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 38 A Source-drain current (pulsed) - 110 A 1.6 V Forward on voltage VGS = 0 V, ISD = 38 A - trr Reverse recovery time - 95 ns Qrr Reverse recovery charge ISD =38 A, di/dt = 100 A/µs, VDD = 60 V - 0.4 µC IRRM Reverse recovery current - 8.5 A - 185 ns - 1.62 µC - 17.5 A VSD trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) ISD = 38 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 15. Test circuit for inductive load switching and diode recovery times) 1. Pulse width is limited by safe operating area. 2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. Table 8. Gate-source Zener diode Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)GSO Gate-source breakdown voltage IGS = ±250 µA, ID = 0 A ±30 - - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DS11238 - Rev 4 page 4/15 STB45N40DM2AG Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area ID (A) Figure 2. Thermal impedance GADG231020181004SOA Operation in this area is limited by R DS(on) 10 2 tp = 1µs tp = 10µs 10 1 tp = 100µs 10 0 tp = 1ms T j ≤150 °C T c = 25°C single pulse 10 -1 10 -1 10 0 tp = 10ms 10 1 VDS (V) 10 2 Figure 3. Output characteristics ID (A) Figure 4. Transfer characteristics ID (A) GIPG270815FQ4LBOCH V GS = 9,10 V 100 80 60 60 V GS = 7 V 40 40 V GS = 6 V 20 0 0 4 8 12 20 V GS = 5 V 16 V DS (V) Figure 5. Gate charge vs gate-source voltage V GS (V) V DS GIPG270815FQ4LBQVG V DS (V) VDD = 320 V, ID = 38 A 12 300 10 250 8 200 6 150 4 100 2 50 DS11238 - Rev 4 V DS = 20 V 100 V GS = 8 V 80 0 0 GIPG270815FQ4LBTCH 10 20 30 40 50 60 0 Q g (nC) 0 2 4 6 8 V GS (V) Figure 6. Static drain-source on-resistance R DS(on) (Ω) GIPG270815FQ4LBRID V GS = 10 V 0.071 0.067 0.063 0.059 0.055 0 8 16 24 32 I D (A) page 5/15 STB45N40DM2AG Electrical characteristics (curves) Figure 8. Normalized gate threshold voltage vs temperature Figure 7. Capacitance variations C (pF) GIPG270815FQ4LBCVR V GS(th) (norm.) 10 4 GIPG270815FQ4LBVTH I D = 250 µA 1.1 C ISS 10 3 C OSS 10 2 1.0 0.9 0.8 f = 1 MHz 10 1 C RSS 0.7 10 10 -1 0 10 0 10 1 10 2 V DS (V) Figure 9. Normalized on-resistance vs temperature R DS(on) (norm.) GIPG190815FQ75A1BRON V GS = 10 V 2.2 0.6 -75 -25 25 75 125 T j (°C) Figure 10. Normalized V(BR)DSS vs temperature V (BR)DSS (norm.) GIPG270815FQ4LBBDV I D = 1 mA 1.12 1.08 1.8 1.04 1.4 1.00 1.0 0.96 0.6 0.2 -75 0.92 -25 25 75 125 T j (°C) Figure 11. Output capacitance stored energy E OSS (µJ) GIPG270815FQ4LBEOS 12 0.88 -75 -25 V SD (V) 125 T j (°C) GIPG270815FQ4LBSDF T j = -50 °C 10 T j = 25 °C 0.8 6 75 Figure 12. Source- drain diode forward characteristics 1.0 8 25 T j = 150 °C 0.6 4 0.4 2 0 0 DS11238 - Rev 4 100 200 300 400 V DS (V) 0.2 0 10 20 30 I SD (A) page 6/15 STB45N40DM2AG Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD RL RL 2200 + μF 3.3 μF VDD VD RG VGS IG= CONST VGS + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v10 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A VD 100 µH fast diode B B B 3.3 µF D G + Figure 16. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) toff td(off) tr tf VD 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS11238 - Rev 4 page 7/15 STB45N40DM2AG Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS11238 - Rev 4 page 8/15 STB45N40DM2AG D²PAK (TO-263) type A2 package information 4.1 D²PAK (TO-263) type A2 package information Figure 19. D²PAK (TO-263) type A2 package outline 0079457_A2_25 DS11238 - Rev 4 page 9/15 STB45N40DM2AG D²PAK (TO-263) type A2 package information Table 9. D²PAK (TO-263) type A2 package mechanical data Dim. mm Min. Typ. Max. A 4.40 4.60 A1 0.03 0.23 b 0.70 0.93 b2 1.14 1.70 c 0.45 0.60 c2 1.23 1.36 D 8.95 9.35 D1 7.50 7.75 8.00 D2 1.10 1.30 1.50 E 10.00 E1 8.70 8.90 9.10 E2 7.30 7.50 7.70 e 10.40 2.54 e1 4.88 5.28 H 15.00 15.85 J1 2.49 2.69 L 2.29 2.79 L1 1.27 1.40 L2 1.30 1.75 R V2 0.40 0° 8° Figure 20. D²PAK (TO-263) recommended footprint (dimensions are in mm) Footprint DS11238 - Rev 4 page 10/15 STB45N40DM2AG D²PAK packing information 4.2 D²PAK packing information Figure 21. D²PAK tape outline DS11238 - Rev 4 page 11/15 STB45N40DM2AG D²PAK packing information Figure 22. D²PAK reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 10. D²PAK tape and reel mechanical data Tape Dim. DS11238 - Rev 4 Reel mm mm Dim. Min. Max. Min. A0 10.5 10.7 A B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 F 11.4 11.6 N 100 K0 4.8 5.0 T Max. 330 13.2 26.4 30.4 P0 3.9 4.1 P1 11.9 12.1 Base quantity 1000 P2 1.9 2.1 Bulk quantity 1000 R 50 T 0.25 0.35 W 23.7 24.3 page 12/15 STB45N40DM2AG Revision history Table 11. Document revision history Date Revision 27-Aug-2015 1 04-Aug-2016 2 14-Feb-2018 3 Changes Initial version Updated Figure 2: "Safe operating area". Minor text changes. Removed maturity status indication from cover page. Updated Section 4.1 D²PAK (TO-263) type A2 package information. Minor text changes Updated Table 1. Absolute maximum ratings and Table 7. Sourcedrain diode. 23-Oct-2018 4 Updated Figure 1. Safe operating area and Figure 14. Test circuit for gate charge behavior. Minor text changes. DS11238 - Rev 4 page 13/15 STB45N40DM2AG Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 [Package name] package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 D²PAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DS11238 - Rev 4 page 14/15 STB45N40DM2AG IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS11238 - Rev 4 page 15/15