STB4N62K3

STB4N62K3, STD4N62K3 N-channel 620 V, 1.7 Ω typ., 3.8 A SuperMESH3™ Power MOSFETs in D²PAK and DPAK packages Datasheet - production data Features Order codes VDS RDS(on) max. ID PW 620 V 2Ω 3.8 A 70 W STB4N62K3 TAB STD4N62K3 TAB • 100% avalanche tested 3 3 1 1 • Extremely high dv/dt capability DPAK D²PAK • Gate charge minimized • Very low intrinsic capacitance • Improved diode reverse recovery characteristics Figure 1. Internal schematic diagram D(2,TAB) • Zener-protected Applications • Switching applications Description G(1) S(3) AM01476v1 These SuperMESH3™ Power MOSFETs are the result of improvements applied to STMicroelectronics’ SuperMESH™ technology, combined with a new optimized vertical structure. These devices boast an extremely low onresistance, superior dynamic performance and high avalanche capability, rendering them suitable for the most demanding applications. Table 1. Device summary Order code Marking Packages STB4N62K3 D²PAK 4N62K3 Tape and reel STD4N62K3 September 2013 This is information on a product in full production. Packaging DPAK DocID18337 Rev 3 1/22 www.st.com Contents STB4N62K3, STD4N62K3 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/22 .............................................. 9 DocID18337 Rev 3 STB4N62K3, STD4N62K3 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 620 V VGS Gate- source voltage ± 30 V ID Drain current (continuous) at TC = 25 °C 3.8 A ID Drain current (continuous) at TC = 100 °C 2 A 15.2 A Total dissipation at TC = 25 °C 70 W IAR Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max) 3.8 A EAS Single pulse avalanche energy (starting Tj = 25°C, ID = IAR, VDD = 50V) 115 mJ IDM (1) PTOT Drain current (pulsed) VESD(G-S) Gate source ESD(HBM-C = 100 pF, R = 1.5 kΩ) 2500 V dv/dt (2) Peak diode recovery voltage slope 12 V/ns VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 °C) Tstg Storage temperature Tj V Max. operating junction temperature - 55 to 150 °C 150 °C 1. Pulse width limited by safe operating area. 2. ISD ≤ 3.8 A, di/dt = 400 A/µs, VDD = 80% V(BR)DSS, VDS peak ≤ V(BR)DSS. Table 3. Thermal data Value Symbol Parameter Unit D²PAK Rthj-case Thermal resistance junction-case max Rthj-pcb (1) Thermal resistance junction-pcb max 30 DPAK 1.79 °C/W 50 °C/W 1. When mounted on 1inch² FR-4 board, 2 oz Cu. DocID18337 Rev 3 3/22 22 Electrical characteristics 2 STB4N62K3, STD4N62K3 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4. On /off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage IDSS Zero gate voltage drain current IGSS Gate-body leakage current VGS = 0, ID = 1 mA Min. Typ. Max. Unit 620 V VGS = 0, VDS = 620V 1 µA VGS = 0 VDS = 620V, TC=125 °C 50 µA ± 10 µA 3.75 4.5 V 1.7 2 Ω Typ. Max. Unit VDS = 0, VGS = ± 20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 50 µA RDS(on Static drain-source onVGS = 10 V, ID = 1.9 A resistance 3 Table 5. Dynamic Symbol Ciss Parameter Test conditions Input capacitance Coss Output capacitance Crss Reverse transfer capacitance VDS = 50 V, f = 1 MHz, VGS = 0 Equivalent output capacitance VDS = 0 to 496 V, VGS = 0 RG Intrinsic gate resistance f = 1 MHz open drain Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Coss eq.(1) Min. VDD = 496 V, ID = 3.8 A, VGS = 10 V (see Figure 18) 2 550 pF 42 pF 7 pF 27 pF 5 Ω 10 22 nC 4 nC 13 nC 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 4/22 DocID18337 Rev 3 STB4N62K3, STD4N62K3 Electrical characteristics Table 6. Switching times Symbol td(on) tr Parameter Test conditions Turn-on delay time VDD = 300 V, ID = 1.9 A, RG = 4.7 Ω, VGS = 10 V (see Figure 17) Rise time td(off) tf Turn-off-delay time Fall time Min. Typ. Max. Unit - 10 - ns - 9 - ns - 29 - ns - 19 - ns Min. Typ. Table 7. Source drain diode Symbol Parameter Test conditions Max. Unit Source-drain current - 3.8 A ISDM (1) Source-drain current (pulsed) - 15.2 A VSD (2) Forward on voltage - 1.6 V ISD trr ISD = 3.8 A, VGS = 0 Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current - 220 ns - 1.4 µC - 13 A - 270 ns - 1.9 µC - 14 A Min Typ. Max. Unit 30 - - V ISD = 3.8 A, di/dt = 100 A/µs VDD = 60 V (see Figure 22) ISD = 3.8 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C (see Figure 22) 1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5% Table 8. Gate-source Zener diode Symbol Parameter Test conditions V(BR)GSO Gate-source breakdown voltage IGS = ± 1mA, ID=0 The built-in back-to-back Zener diodes have been specifically designed to enhance not only the device’s ESD capability, but also to make them capable of safely absorbing any voltage transients that may occasionally be applied from gate to source. In this respect, the Zener voltage is appropriate to achieve efficient and cost-effective protection of device integrity. The integrated Zener diodes thus eliminate the need for external components. DocID18337 Rev 3 5/22 22 Electrical characteristics 2.1 STB4N62K3, STD4N62K3 Electrical characteristics (curves) Figure 2. Safe operating area for D²PAK Figure 3. Thermal impedance for D²PAK AM07172v1 ID (A) 10 is 10µs D S( on ) O Li per m at ite io d ni by n m this ax a R rea 100µs 1 1ms 10ms 0.1 Tj=150°C Tc=25°C Single pulse 0.01 0.1 10 1 100 VDS(V) Figure 4. Safe operating area for DPAK 10 10µs Figure 5. Thermal impedance for DPAK on ) 100µs D S( O Li per m at ite io d ni by n m this ax a R rea is ID (A) AM07173v1 1 1ms 10ms Tj=150°C Tc=25°C 0.1 Single pulse 0.01 0.1 10 1 100 VDS(V) Figure 6. Output characteristics Figure 7. Transfer characteristics AM07175v1 ID (A) 8 VGS=10V 7V 7 AM07176v1 ID (A) VDS=15V 6 5 6 4 5 4 6V 3 3 2 2 1 1 5V 0 0 6/22 5 10 15 20 25 VDS(V) DocID18337 Rev 3 0 0 2 4 6 8 VGS(V) STB4N62K3, STD4N62K3 Electrical characteristics Figure 8. Gate charge vs gate-source voltage AM07177v1 VGS (V) VDS 12 VGS VDD=496V ID=3.8A Figure 9. Static drain-source on resistance AM07178v1 RDS(on) (Ω) VGS=10V 500 10 1.9 400 1.8 8 300 6 1.7 200 4 1.6 100 2 0 0 10 5 20 15 0 25 Qg(nC) Figure 10. Capacitance variations 2 1 3 ID(A) Figure 11. Output capacitance stored energy AM07179v1 C (pF) 1.5 0 AM07180v1 Eoss (µJ) 3.0 1000 2.5 Ciss 2.0 100 1.5 Coss 1.0 10 Crss 0.5 1 0.1 1 100 10 Figure 12. Normalized gate threshold voltage vs temperature AM07181v1 VGS(th) 0 0 VDS(V) (norm) 100 200 300 400 500 600 VDS(V) Figure 13. Normalized on-resistance vs temperature AM07182v1 RDS(on) (norm) 1.10 2.5 2.0 1.00 1.5 0.90 1.0 0.80 0.70 -75 0.5 -25 25 75 125 TJ(°C) DocID18337 Rev 3 -75 -25 25 75 125 TJ(°C) 7/22 22 Electrical characteristics STB4N62K3, STD4N62K3 Figure 14. Maximum avalanche energy vs starting Tj EAS (mJ) 120 110 100 90 80 70 60 50 40 30 20 10 0 0 AM07184v1 ID=3.8 A VDD=50 V Figure 15. Normalized BVDSS vs temperature 1.10 1.05 1.00 0.95 20 40 60 80 100 120 140 TJ(°C) 0.90 -75 Figure 16. Source-drain diode forward characteristics VSD (V) 1.0 AM08888v1 TJ=150°C TJ=25°C 0.9 0.8 0.7 TJ=-50°C 0.6 0.5 0.4 0.3 0.2 0.1 0 8/22 AM07183v1 BVDSS (norm) 1 2 3 4 5 ISD(A) DocID18337 Rev 3 -25 25 75 125 TJ(°C) STB4N62K3, STD4N62K3 3 Test circuits Test circuits Figure 17. Switching times test circuit for resistive load Figure 18. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF IG=CONST VDD VGS 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 Figure 19. Test circuit for inductive load switching and diode recovery times A A AM01469v1 Figure 20. Unclamped Inductive load test circuit L A D G D.U.T. FAST DIODE B B VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 21. Unclamped inductive waveform Figure 22. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 0 DocID18337 Rev 3 10% AM01473v1 9/22 22 Package mechanical data 4 STB4N62K3, STD4N62K3 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 10/22 DocID18337 Rev 3 STB4N62K3, STD4N62K3 Package mechanical data Table 9. D²PAK (TO-263) mechanical data mm Dim. Min. Typ. Max. A 4.40 4.60 A1 0.03 0.23 b 0.70 0.93 b2 1.14 1.70 c 0.45 0.60 c2 1.23 1.36 D 8.95 9.35 D1 7.50 E 10 E1 8.50 10.40 e 2.54 e1 4.88 5.28 H 15 15.85 J1 2.49 2.69 L 2.29 2.79 L1 1.27 1.40 L2 1.30 1.75 R V2 0.4 0° 8° DocID18337 Rev 3 11/22 22 Package mechanical data STB4N62K3, STD4N62K3 Figure 23. D²PAK (TO-263) drawing 0079457_T Figure 24. D²PAK footprint(a) 16.90 12.20 5.08 1.60 3.50 9.75 a. All dimension are in millimeters 12/22 DocID18337 Rev 3 Footprint STB4N62K3, STD4N62K3 Package mechanical data Table 10. DPAK (TO-252) type A mechanical data mm Dim. Min. Typ. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 E 5.10 6.40 6.60 E1 4.70 e 2.28 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 (L1) 2.80 L2 0.80 L4 0.60 1.00 R V2 0.20 0° 8° DocID18337 Rev 3 13/22 22 Package mechanical data STB4N62K3, STD4N62K3 Figure 25. DPAK (TO-252) type A drawing 0068772_K_type_A 14/22 DocID18337 Rev 3 STB4N62K3, STD4N62K3 Package mechanical data Table 11. DPAK (TO-252) type E mechanical data mm Dim. Min. A Typ. 2.18 Max. 2.39 A2 0.13 b 0.65 0.884 b4 4.95 5.46 c 0.46 0.61 c2 0.46 0.60 D 5.97 6.22 D1 5.21 E 6.35 E1 4.32 6.73 e 2.286 e1 4.572 H 9.94 10.34 L 1.50 1.78 L1 L2 2.74 0.89 1.27 L4 1.02 DocID18337 Rev 3 15/22 22 Package mechanical data STB4N62K3, STD4N62K3 Figure 26. DPAK (TO-252) type E drawing 0068772_K_type_E 16/22 DocID18337 Rev 3 STB4N62K3, STD4N62K3 Package mechanical data Figure 27. DPAK footprint (b) Footprint_REV_K b. All dimensions are in millimeters DocID18337 Rev 3 17/22 22 Packaging mechanical data 5 STB4N62K3, STD4N62K3 Packaging mechanical data Table 12. D²PAK (TO-263) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. Min. Max. A0 10.5 10.7 A B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 F 11.4 11.6 N 100 K0 4.8 5.0 T P0 3.9 4.1 P1 11.9 12.1 Base qty 1000 P2 1.9 2.1 Bulk qty 1000 R 50 T 0.25 0.35 W 23.7 24.3 330 13.2 26.4 30.4 Table 13. DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 18/22 Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 DocID18337 Rev 3 18.4 22.4 STB4N62K3, STD4N62K3 Packaging mechanical data Table 13. DPAK (TO-252) tape and reel mechanical data (continued) Tape Reel mm mm Dim. Dim. Min. Max. P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 Min. Max. Figure 28. Tape for D²PAK (TO-263) and DPAK (TO-252) 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 K0 For machine ref. only including draft and radii concentric around B0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 DocID18337 Rev 3 19/22 22 Packaging mechanical data STB4N62K3, STD4N62K3 Figure 29. Reel for D²PAK (TO-263) and DPAK (TO-252) T REEL DIMENSIONS 40mm min. Access hole At slot location B D C N A Full radius Tape slot in core for tape start 25 mm min. width G measured at hub AM08851v2 20/22 DocID18337 Rev 3 STB4N62K3, STD4N62K3 6 Revision history Revision history Table 14. Document revision history Date Revision Changes 16-Dec-2010 1 First release. 26-Apr-2012 2 Added min and max values for RG in Table 5: Dynamic and Section 5: Packaging mechanical data. Updated Section 4: Package mechanical data. Minor text changes. 09-Sep-2013 3 – Updated: Section 4: Package mechanical data – Minor text changes DocID18337 Rev 3 21/22 22 STB4N62K3, STD4N62K3 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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