STCF06
1.5 A white LED driver with I²C interface
Features
■
Buck-boost DC-DC converter
■
Drives one power LED up to:
– 1.5 A between 3.5 V to 5.5 V
– 1.3 A between 3.0 V to 5.5 V
– 1 A between 2.7 V to 5.5 V
■
Efficiency up to 80%
■
Output current control
■
1.8 MHz fixed frequency PWM
■
Full I²C control
■
Operational modes:
– Shutdown mode
– Ready mode + auxiliary red LED
– Ready mode + NTC
– Flash mode: up to 1.5 A
– Torch mode: up to 370 mA
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TFBGA25 (3 x 3 mm)
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Soft and hard triggering of flash
■
Flash and torch dimming with 16 exponential
values
■
Dimmable red LED indicator auxiliary output
■
Internally or externally timed flash operation
■
Digitally programmable safety time-out in flash
mode
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LED over temperature detection and protection
with external NTC resistor
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Open and shorted LED failure detection and
protection
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Chip over temperature detection and protection
■
< 1 µA shutdown current
■
Package 3 x 3 mm TFBGA25
Table 1.
July 2010
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Cell phones and smart phones
■
Camera flashes/strobe
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PDAs and digital still cameras
The STCF06 is a high efficiency power supply
solution to drive a single flash LED in camera
phones, PDAs and other battery powered
devices. It is a buck-boost converter able to
guarantee a proper LED current control over all
possible conditions of battery voltage and LED
forward voltage. The output current control
ensures a good current regulation over the
forward voltage spread characteristics of the flash
LED. All the functions of the device are controlled
through the I²C bus which helps to reduce logic
pins on the package and to save PCB tracks on
the board. Hard and soft-triggering of flash are
both supported. The device includes many
functions to protect the chip and the power LED,
such as: soft start control, chip over temperature,
open and shorted LED detection and protection.
Device summary
Order code
Package
Packaging
STCF06TBR
TFBGA25 (3 x 3 mm)
3500 parts per reel
Doc ID 14549 Rev 3
1/35
www.st.com
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Contents
STCF06
Contents
1
Description (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7
Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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7.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2
Buck-boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.3
Logic pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.3.1
SCL, SDA pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.3.2
TRIG pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.3.3
ATN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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ADD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.3.5
TMSK pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.4
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.5
Shutdown, shutdown with NTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.6
Ready mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.7
Single or multiple flash using external (microprocessor) temporization . . 15
7.8
External (microprocessor) temporization using TRIG_EN bit . . . . . . . . . 15
7.9
Single flash using internal temporization . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.10
Multiple flash using internal temporization . . . . . . . . . . . . . . . . . . . . . . . . 16
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I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8.1
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8.2
Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8.3
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Doc ID 14549 Rev 3
STCF06
9
Contents
8.4
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.5
Writing to a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.6
Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.7
Writing to multiple registers with incremental addressing . . . . . . . . . . . . 20
8.8
Reading from a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.9
Reading from multiple registers with incremental addressing . . . . . . . . . 21
Description of internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.1
PWR_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.2
TRIG_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.3
TCH_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.4
NTC_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.5
FTIM_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.6
TDIM_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.7
FDIM_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.8
AUXI_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.9
AUXT_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.10
F_RUN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9.11
LED_F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9.12
NTC_W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.13
NTC_H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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OT_F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
VOUTOK_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Doc ID 14549 Rev 3
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List of tables
STCF06
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
List of external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
I²C register mapping function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Dimming register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Auxiliary register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Auxiliary LED dimming table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Torch mode and flash mode dimming registers settings . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Status register details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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Doc ID 14549 Rev 3
STCF06
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data validity on the I²C bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Timing diagram on I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Acknowledge on I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Writing to a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Writing to multiple register with incremental addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reading from a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reading from multiple registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Flash and torch current vs. dimming value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
VOUTOK_N behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Efficiency vs. VBAT flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Efficiency vs. VBAT, torch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Maximum output current vs. VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Flash current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Input current vs. VBAT (VLED = 3.75 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Input current vs. VBAT (ILED = 1 A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ILED flash vs. FDIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
ILED torch vs. TDIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Flash time dimming steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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Description (continued)
1
STCF06
Description (continued)
In addition, a digital programmable time-out function protects the LED in case of a wrong
command from the microcontroller. An optional external NTC resistor is supported to protect
the LED against over heating.
In mobile phone applications, it is possible to reduce immediately the flash LED current
during the signal transmission using the TMSK pin. This saves battery life and gives more
priority to supply RF transmission instead of flash function.
Dedicated I²C commands allow to separately program the current intensity in flash and torch
mode using exponential steps. An auxiliary output controls an optional red LED to be used
as a recording indicator.
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The device is packaged in 3 x 3 mm TFBGA25 with 1 mm height.
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Doc ID 14549 Rev 3
STCF06
Diagram
2
Diagram
Figure 1.
Block diagram
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Pin configuration
STCF06
3
Pin configuration
Figure 2.
Pin connections (top view)
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Table 2.
Pin n°
Symbol
E1,D2
VLX2
B3
RX
D1,C2
VOUT
A4
NTC
NTC resistor connection
B5
FB1
Feedback pin [ILED*(RFL+RTR)]
A5
FB2
B4
FB2S
Name and function
Inductor connection
RX resistor connection
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Output voltage
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GND
C5
RTR bypass
Feedback pin [ILED*RFL]
Signal ground
TMSK
TX mask input
AUXL
Auxiliary LED output
D4
ADD
I²C address selection
A3
VBAT
Supply voltage
B1,C1
PVBAT
Power supply voltage
A2
VLX1A
Inductor connection
A1, B2
VLX1B
Inductor connection
E4
ATN
Attention (open drain output, active LOW)
E3
SDA
I²C data
C3, D3
PGND
E5
SCL
I²C clock signal
C4
TRIG
Flash trigger input
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Pin description
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Power ground
Doc ID 14549 Rev 3
STCF06
Maximum ratings
4
Maximum ratings
Table 3.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VBAT
Signal supply voltage
-0.3 to 6
V
PVBAT
Power supply voltage
-0.3 to 6
V
VLX1A, VLX1B
Inductor connection 1
–0.3 to VI+0.3
V
VLX2
Inductor connection 2
–0.3 to VO+0.3
V
VOUT
Output voltage
-0.3 to 6
V
AUXL
Auxiliary LED
–0.3 to VBAT+0.3
FB1, FB2, FB2S
Feedback and sense voltage
SCL, SDA, TRIG,
ATN, ADD TMSK
Logic pin
RX
-0.3 to 3
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-0.3 to VBAT+0.3
NTC
Connection for LED Temperature sensing
ESD
Human body model
PTOT
Continuous power dissipation (at TA = 70°C)
TOP
Operating junction temperature range
t(s
Storage temperature range
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Junction temperature
TSTG
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Connection for reference resistor
TJ
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V
V
-0.3 to 3
V
-0.3 to 3
V
±2
kV
800
mW
-40 to 85
°C
-40 to 150
°C
-65 to 150
°C
Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these condition is not implied.
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Table 4.
Symbol
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Thermal data
Parameter
Thermal resistance junction-ambient
Doc ID 14549 Rev 3
Value
Unit
58
°C/W
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Application
STCF06
5
Application
Figure 3.
Application schematic
CO
4.7µF
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**: Connect to VI, or GND or SDA or SCL to choose one of the 4 different I²C Slave Addresses.
***: Optional components to support auxiliary functions. Vref_ext = 1.8 V
Table 5.
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List of external components
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Component
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CI
Manufacturer
Part number
Value
Size
TDK
C1608X5R0J106M
2 x 10 µF
0603
TDK
C1608X5R0J475M
4.7 µF
0603
L (max flash 1.5 A)
TDK
VLF4014A-1R51R8-1
1.5 µH
3.8x3.5x1.4 [mm]
NTC
Murata
NCP21WF104J03RA
100 kΩ
0805
RFL
Tyco
RL73K1JR15JTD
0.15 Ω
0603
RTR
Tyco
CRG0805F1R0
1Ω
0805
RX
Rohm
MCR01MZPJ15K
15 kΩ
0402
LED
Luxeon LED
LXCL-PWF1
D
STMicroelectro
nics
CO
o
s
b
O
STPS1L20MF
(best performance)
3.8x1.9x0.85 [mm]
BAT20J (1) (smaller size)
2.7x1.35x1.13 [mm]
1. Due to the increased voltage drop, the output current performance is decreased.
Note:
10/35
All of the above listed components refer to typical application. Operation of the STCF06 is
not limited to the choice of these external components.
Doc ID 14549 Rev 3
STCF06
Electrical characteristics
6
Electrical characteristics
TJ = -40 to 85 °C, VBAT = PVBAT = 3.6 V, 2 x CI = 10 µF, CO = 4.7 µF, L = 1.5 µH, RFL = 0.15
Ω, RTR = 1 Ω, RX = 15 kΩ, typ. values are at TJ = 25 °C, unless otherwise specified.
Table 6.
Electrical characteristics
Symbol
Parameter
VI
Input operation supply voltage
VPW_ON
Test condition
Power-ON reset threshold
Output current adjustment
range IFLASH
2.7
Flash mode for VI = 3.5 V to 5.5 V
117
Flash mode for VI = 3.0 V to 3.3 V
117
Flash mode for VI = 2.7 V to 5.5 V
117
Output current adjustment
range ITORCH
Torch mode VI = 2.7 V to 5.5 V
Auxiliary LED output current
adjustment range IAUXLED
Ready mode, VI = 2.7 V to 5.5 V
e
t
e
l
Regulated voltage range
FB1
Feedback voltage
Torch mode
FB2
Feedback voltage
Flash mode
ΔIO
Output current tolerance
RON_
FB1-FB2 ON resistance
)
s
(
ct
o
s
b
-O
Flash mode, IO = 160 mV/RFL
OVHYST
)
s
(
ct
1500
1300
29
0
20
o
r
P
1000
mA
370
2.5
5.0
V
30
250
mV
30
250
mV
-10
10
%
Torch mode, IO = 200 mA
1
µA
1.8
mA
VI = 2.7 V
1.8
MHz
Efficiency of the chip itself (1)
VI = 3.2 to 4.2 V, Flash Mode,
IO = 2200 mA
80
Efficiency of the whole
application (2)
VI = 3.2 to 4.2 V, Flash Mode,
IO = 2200 mA, VO=VfLED_max + VFB2 =
5.02 V
See the typical application schematic
It is included losses of inductor and
sensing resistor
du
o
r
P
ete
ol
OVP
V
mΩ
Frequency
ν
5.5
V
du
Quiescent current in ready mode
s
b
O
Unit
90
Quiescent current in
SHUTDOWN mode
fs
Max.
2.3
VO
IQ
Typ.
VI rising
RESET
IO
Min.
Output over voltage protection VI = 5.5 V, No Load
Over voltage hysteresis
VI = 5.5 V, No Load
%
70
5.3
V
0.2
V
OTP
Junction over temperature
protection
140
°C
OTHYST
Junction over temperature
hysteresis
20
°C
VREF5
NTC hot voltage threshold
1.2
V
Ready mode, INTC = 2mA max
Doc ID 14549 Rev 3
11/35
Electrical characteristics
Table 6.
STCF06
Electrical characteristics (continued)
Symbol
Parameter
Test condition
VREF4
NTC warning voltage
threshold
RONT1
RX-NTC switch ON resistance Ready mode
Min.
Ready mode, INTC = 2mA max
Typ.
NTCLEAK RX-NTC switch OFF leakage
Max.
Unit
0.56
V
25
Ω
Shutdown mode, VNTC = 2 V
VRX = GND
1
µA
VOL
Output logic signal level low
ATN
IOL = 10 mA
0.2
V
IOZ
Output logic leakage current
ATN
VOZ = 3.3 V
1
mA
Input logic signal level SCL,
SDA, TRIG, TMSK, ADD
VI = 2.7 V to 5.5 V
VIL
VIH
V
u
d
o
r
P
e
1. Calculated as (VO*ILED)/(VIN*IIN)
t
e
l
o
2. Calculated as (VLED*ILED)/(VIN*IIN)
)
(s
s
b
O
t
c
u
d
o
r
P
e
t
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o
s
b
O
12/35
0.4
1.4
LED current rise time
ILED = 0 to ILED = max
TON
)
s
(
ct
0
Doc ID 14549 Rev 3
3
2
ms
STCF06
Detailed description
7
Detailed description
7.1
Introduction
The STCF06 is a buck-boost converter, dedicated to power and control the current of a
power white LED in a camera cell phone. The device operates at a typical constant
switching frequency of 1.8 MHz. It regulates the LED current up to 1.5 A and supports LED
with forward voltage ranging from 2.5 V to 5.0 V. The input voltage supply range from 2.7 V
to 5.5 V allows operation from a single cell Lithium-Ion battery. The I²C bus is used to control
the device operation and for diagnostic purposes. The current in torch mode is adjustable up
to 370 mA. Flash mode current is adjustable up to 1500mA for an input voltage higher than
3.5 V, 1300 mA for an input voltage of 3.0 V at least and 1000 mA when the input voltage is
2.7 V. The Aux LED current can be adjusted from 0 to 20 mA. The device uses an external
NTC resistor to sense the temperature of the white LED. These two last functions may not
be needed in all applications, and in these cases the relevant external components can be
omitted.
)
s
(
ct
7.2
u
d
o
r
P
e
Buck-boost converter
t
e
l
o
The regulation of the PWM controller is done by sensing the current of the LED through
external sensing resistors (RFL and RTR, see application schematic). Depending on the
forward voltage of the flash LED, the device automatically can change the operation mode
between buck (step down) and boost (step up) mode.
)
(s
s
b
O
Three cases can occur: Boost region (VO > VBAT): this configuration is used in most of the
cases, as the output voltage VO = VfLED + ILED x RFL is higher than VBAT; Buck region (VO <
VBAT); Buck / Boost region (VO ~ VBAT).
7.3
t
c
u
Logic pin description
d
o
r
P
e
t
e
ol
7.3.1
s
b
O
7.3.2
7.3.3
SCL, SDA pins
These are the standard clock and data pins as defined in the I²C bus specification. External
pull-up is required according to I²C bus specifications. The recommended maximum voltage
of these signals should be 3.0 V.
TRIG pin
This input pin is internally AND-ed with the TRIG_EN bit to generate the internal signal that
activates the flash operation. This gives to the user the possibility to accurately control the
flash duration using a dedicated pin, avoiding the I²C bus latencies (hard-triggering). No
internal pull-up nor pull-down is provided.
ATN pin
This output pin (open-drain, active LOW) is provided to better manage the information
transfer from the STCF06 to the microprocessor. Because of the limitations of a single
master I²C bus configuration, the microprocessor should regularly poll the STCF06 to verify
if certain operations have been completed, or to check diagnostic information. Alternatively,
Doc ID 14549 Rev 3
13/35
Detailed description
STCF06
the microprocessor can use the ATN pin to be advised that new data are available in the
STAT_REG, thus avoiding continuous polling. Then the information can be read in the
STAT_REG by a read operation via I²C that, besides, automatically resets the ATN pin. The
STAT_REG bits affecting the ATN pin status are mapped in Table 15. No internal pull-up is
provided.
7.3.4
ADD pin
With this pin it is possible to select one of the 4 possible I²C slave addresses. No internal
pull-up nor pull-down is provided. The pin has to be connected to either GND, VI,SCL or
SDA to select the desired I²C slave address (see Table 7)
Table 7.
Address table
ADD pin
A7
A6
A5
A4
A3
A2
A1
GND
0
1
1
0
0
0
0
VBAT
0
1
1
0
0
0
SDA
0
1
1
0
0
1
SCL
0
1
1
0
0
1
od
7.3.5
TMSK pin
e
t
e
ol
Pr
uc
)
s
(
t
A0
R/W
1
R/W
0
R/W
1
R/W
s
b
O
This pin can be used to implement the TX masking function. This function has effect only for
flash current settings higher than 370 mA (bit FDIM=7hex). Under this condition, when this
pin is pulled high by the microprocessor, the current flowing in the LED is forced at 370 mA
typ. No internal pull-up or pull-down is provided; to be externally wired to GND if TX masking
function is not used. The value corresponds to RFL resistor 0.15 ohm.
)
(s
7.4
t
c
u
Power-on reset
d
o
r
P
e
t
e
l
o
s
b
O7.5
This mode is initiated by applying a supply voltage above the VPW_ON RESET threshold
value. An internal timing (~1 µs) defines the duration of this status. The logic blocks are
powered, but the device doesn't respond to any input. The registers are reset to their default
values, the ATN and SDA pins are in high-Z, and the I²C slave address is internally set by
reading the ADD pin configuration. After the internally defined time has elapsed, the
STCF06 automatically enters the Stand-by mode.
Shutdown, shutdown with NTC
In this mode only the I²C interface is alive, accepting I²C commands and register settings.
The device enters this mode: automatically from power-on reset status; by resetting the
PWR_ON bit from other operation modes. Power consumption is at the minimum (1 µA max)
if NTC is not activated (NTC_ON=0). If PWR_ON and NTC_ON is set, the T1 is switched
ON (see Figure 1), allowing the microprocessor to measure the LED temperature through its
A/D converter.
14/35
Doc ID 14549 Rev 3
STCF06
7.6
Detailed description
Ready mode
In this mode all internal blocks are turned ON, but the DC-DC converter is disabled and the
White LED is disconnected. The NTC circuit can be activated to monitor the temperature of
the LED and I²C commands and register settings are allowed to be executed immediately.
Only in this mode the auxiliary LED is operational and can be turned ON and set at the
desired brightness using the AUX REGISTER. The device enters this mode: from Stand-by
by setting the PWR_ON bit; from flash operation by resetting the TRIG pin or the TRIG_EN
bit or automatically from flash operation when the time counter reaches zero; from torch
operation by resetting the TCH_ON bit. The device automatically enters this mode also
when an overload or an abnormal condition has been detected during flash or torch
operation (Table 16: Status register details:).
)
s
(
ct
7.7
Single or multiple flash using external (microprocessor)
temporization
u
d
o
To avoid the I²C bus time latency, it is recommended to use the dedicated TRIG pin to define
the flash duration (hard-triggering). The TRIG_EN bit of CMD_REG should be set before
starting each flash operation, because it could have been reset automatically in the previous
flash operation. The flash duration is determined by the pulse length that drives the TRIG
pin. As soon as the flash is activated, the system needs typically 1.2 ms to ramp up the
output current on the Power LED. The internal time counter will time-out flash operation and
keep the LED dissipated energy within safe limits in case of Software deadlock; FTIM
register has to be set first, either in Stand-by or in ready mode. Multiple flashes are possible
by strobing the TRIG pin. Time out counter will cumulate every flash on-time until the
defined time out is reached unless it is reloaded by updating the CMD_REG. After a single
or multiple flash operations are timed-out, the device automatically goes into Ready mode
by resetting the TRIG_EN bit, and also resets the F_RUN bit. The ATN pin is pulled down to
inform the microprocessor that the STAT_REG has been updated.
r
P
e
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
7.8
External (microprocessor) temporization using TRIG_EN bit
P
e
t
e
l
o
s
b
O
7.9
Even if it is possible, it is not recommended to use the TRIG_EN bit to start and stop the
flash operation, because of I²C bus latencies: this would result in inaccurate flash timing.
Nevertheless, if this operation mode is chosen, the TRIG pin has to be kept High (logic level
or wired to VBAT), leaving the whole flash control to the I²C bus. Also in this operation mode
the Time Counter will Time-out flash operation and keep the energy dissipated by the LED
within safe limits in case of SW deadlock.
Single flash using internal temporization
Flash triggering can be obtained either by TRIG pin (hard-triggering) or by I²C commands
(soft-triggering). The first solution is recommended for an accurate start time, while the
second is less accurate because of the I²C bus time latency. Stop time is defined by the
STCF06 internal temporization and its accuracy is determined by the internal oscillator. For
hard-triggering, it is necessary to set the TRIG_EN bit in advance. For soft-triggering, the
TRIG pin has to be kept High (logic level or wired to VBAT) and the flash can be started by
setting the FTIM and the TRIG_EN through I²C (both are located in the CMD REG). There is
a delay time between the moment the flash is triggered and when it appears. This delay is
Doc ID 14549 Rev 3
15/35
Detailed description
STCF06
caused by the time necessary to charge up the output capacitor, which is around 1.2 ms
depending on battery voltage and output current value. Once triggered, the flash operation
will be stopped when the time counter reaches zero. As soon as the flash is finished, the
F_RUN bit is reset, the ATN pin is pulled down for 11 µs to inform the microprocessor that
the STAT_REG has been updated and the device goes back to Ready mode. If it is
necessary to make a flash longer than the internal timer allows or a continuous flash, then
the FTIM must be reloaded through I²C bus every time, before the internal timer reaches
zero. For example: To get a continuous flash, set FTIM to 1.5 s and every 1 s reload the
CMD_REG.
7.10
Multiple flash using internal temporization
)
s
(
ct
This operation has to be processed as a sequence of single flashes using internal
temporization starting from hard or soft triggering. Since the TRIG_EN bit is reset at the end
of each flash, it is necessary to reload the CMD_REG to start the next one.
u
d
o
r
P
e
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
P
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t
e
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o
s
b
O
16/35
Doc ID 14549 Rev 3
STCF06
8
I²C bus interface
I²C bus interface
Data transmission from the main microprocessor to STCF06 and vice versa takes place
through the 2 I²C bus interface wires, consisting of the two lines SDA and SCL (pull-up
resistors to a positive supply voltage must be externally connected). The recommended
maximum voltage of these signals should be 3.0 V.
8.1
Data validity
As shown in Figure 4, the data on the SDA line must be stable during the high period of the
clock. The HIGH and LOW state of the data line can only change when the clock signal on
the SCL line is LOW.
Figure 4.
)
s
(
ct
Data validity on the I²C bus
u
d
o
r
P
e
t
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l
o
)
(s
s
b
O
t
c
u
d
o
r
8.2
Start and stop conditions
P
e
Both DATA and CLOCK lines remain HIGH when the bus is not busy. As shown in Figure 5 a
start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop
condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP condition
must be sent before each START condition.
s
b
O
t
e
l
o
Doc ID 14549 Rev 3
17/35
I²C bus interface
Figure 5.
STCF06
Timing diagram on I²C bus
)
s
(
ct
8.3
u
d
o
Byte format
r
P
e
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first. One data bit is transferred during each clock
pulse. The data on the SDA line must remain stable during the HIGH period of the clock
pulse. Any change in the SDA line at this time will be interpreted as a control signal.
t
e
l
o
Figure 6.
)
(s
Bit transfer
s
b
O
t
c
u
d
o
r
P
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t
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o
s
b
O
8.4
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see Figure 7). The peripheral (STCF06) that acknowledges has to
pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is
stable LOW during this clock pulse. The peripheral which has been addressed has to
generate an acknowledge pulse after the reception of each byte, otherwise the SDA line
remains at the HIGH level during the ninth clock pulse duration. In this case, the master
transmitter can generate the STOP information in order to abort the transfer.
18/35
Doc ID 14549 Rev 3
STCF06
I²C bus interface
Figure 7.
Acknowledge on I²C bus
Table 8.
)
s
(
ct
Device address + R/W bit
7
6
u
d
o
Interface protocol
5
4
S
T M
A S
R B
T
3
2
1
0
Register address
7
6
5
4
3
2
L
A M
R
S
C S
W
B
K B
Data
1
r
P
e
0
7
L
S
B
let
o
s
b
A M
C S
K B
6
5
4
3
2
1
0
L
S
B
A
C
K
S
T
O
P
O
)
8.5
Writing to a single register
s
(
t
c
Writing to a single register starts with a START bit followed by the 7 bit device address of
STCF06. The 8th bit is the R/W bit, which is 0 in this case. R/W = 1 means a reading
operation. Then the master waits for an acknowledge from STCF06. Then the 8 bit address
of register is sent to STCF06. It is also followed by an acknowledge pulse. The last
transmitted byte is the data that is going to be written to the register. It is again followed by
an acknowledge pulse from STCF06. Then master generates a STOP bit and the
communication is over. See Figure 8 below.
u
d
o
r
P
e
t
e
l
o
s
b
O
Doc ID 14549 Rev 3
19/35
I²C bus interface
Figure 8.
STCF06
Writing to a single register
W
R
I
T
E
DEVICE
ADDRESS
7 bits
S M
T S
A B
R
T
ADDRESS OF
REGISTER
L R A M
S / C S
B W K B
DATA
L A M
S C S
B K B
L A S
S C T
B K O
P
)
s
(
ct
SDA LINE
u
d
o
8.6
r
P
e
t
e
l
o
Interface protocol
The interface protocol is composed:
- A start condition (START)
s
b
O
- A Device address + R/W bit (read =1 / write =0)
)
(s
- A Register address byte
t
c
u
- A sequence of data n* (1 byte + acknowledge)
- A stop condition (STOP)
d
o
r
The Register address byte determines the first register in which the read or write operation
takes place. When the read or write operation is finished, the register address is
automatically increased.
P
e
8.7
s
b
O
t
e
l
o Writing to multiple registers with incremental addressing
20/35
It would be unpractical to send several times the device address and the address of the
register when writing to multiple registers. STCF06 supports writing to multiple registers with
incremental addressing. When the data is written to a register, the address register is
automatically increased, so the next data can be sent without sending the device address
and the register address again. See Figure 9 below.
Doc ID 14549 Rev 3
STCF06
I²C bus interface
Figure 9.
Writing to multiple register with incremental addressing
W
R
I
T
E
DEVICE
ADDRESS
7 bits
S M
T S
A B
R
T
ADDRESS OF
REGISTER i
L R A M
S / C S
B W K B
DATA i
L A M
S C S
B K B
DATA i+1
L A M
S C S
B K B
DATA i+2
L A M
S C S
B K B
DATA i+2
DATA i+n
L A M
S C S
B K B
L A M
S C S
B K B
L A S
S C T
B K O
P
)
s
(
ct
SDA LINE
8.8
u
d
o
r
P
e
Reading from a single register
The reading operation starts with a START bit followed by the 7 bit device address of
STCF06. The 8th bit is the R/W bit, which is 0 in this case. STCF06 confirms the receiving of
the address + R/W bit by an acknowledge pulse. The address of the register which should
be read is sent afterwards and confirmed again by an acknowledge pulse of STCF06 again.
Then the master generates a START bit again and sends the device address followed by the
R/W bit, which is 1 now. STCF06 confirms the receiving of the address + R/W bit by an
acknowledge pulse and starts to send the data to the master. No acknowledge pulse from
the master is required after receiving the data. Then the master generates a STOP bit to
terminate the communication. See Figure 10
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
Figure 10. Reading from a single register
P
e
t
e
l
o
s
b
O
DEVICE
ADDRESS
7 bits
S M
T S
A B
R
T
W
R
I
T
E
L R A M
S / C S
B WK B
ADDRESS
OF
REGISTER
DEVICE
ADDRESS
7 bits
L A S
S C T
B K A
R
T
R
E
A
D
R A
/ C
WK
DATA
L N S
S O T
O
B
A P
C
K
SDA LINE
8.9
Reading from multiple registers with incremental addressing
Reading from multiple registers starts in the same way like reading from a single register. As
soon as the first register is read, the register address is automatically increased. If the
master generates an acknowledge pulse after receiving the data from the first register, then
Doc ID 14549 Rev 3
21/35
I²C bus interface
STCF06
reading of the next register can start immediately without sending the device address and
the register address again. The last acknowledge pulse before the STOP bit is not required.
See the Figure 11.
Figure 11. Reading from multiple registers
DEVICE
ADDRESS
7 bits
S M
T S
A B
R
T
W
R
I
T
E
DEVICE
ADDRESS
7 bits
ADDRESS OF
REGISTER i
L R A M
S / C S
B W K B
L A S
S C T
B K A
R
T
R
E
A
D
DATA i
DATA i+1
L A M
S C S
B K B
DATA i+2
R A
/ C
W K
L A M
S C S
B K B
DATA i+2
L A M
S C S
B K B
u
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P
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o
s
b
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c
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t
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s
b
O
22/35
Doc ID 14549 Rev 3
)
s
(
ct
L A M
S C S
B K B
SDA LINE
)
(s
DATA i+n
L N S
S O T
O
B
A P
C
K
STCF06
Description of internal registers
9
Description of internal registers
Table 9.
I²C register mapping function
Table 10.
Register name
SUB ADDRESS (hex)
Operation
CMD_REG
00
R/W
DIM_REG
01
R/W
AUX_REG
02
R/W
STAT_REG
03
R only
)
s
(
ct
Command register
CMD_REG
(write mode)
MSB
SUB ADD=00
PWR_ON
TRIG_EN
TCH_ON
NTC_ON
Power-ON
RESET Value
0
0
0
0
9.1
FTIM_3
e
t
e
l
0
u
d
o
Pr
LSB
FTIM_2
FTIM_1
FTIM_0
0
0
0
o
s
b
PWR_ON
O
)
When set, it activates all analog and power internal blocks including the NTC supporting
circuit, and the device is ready to operate (ready mode). As long as PWR_ON=0, only the
I²C interface is active, minimizing Stand-by Mode power consumption.
s
(
t
c
u
d
o
9.2
TRIG_EN
r
P
e
This bit is AND-ed with the TRIG pin to generate the internal signal FL_ON that activates
flash mode. By this way, both soft-triggering and hard-triggering of the flash are made
possible. If soft-triggering (through I²C) is chosen, the TRIG pin is not used and must be
kept HIGH (VI). If hard-triggering is chosen, then the TRIG pin has to be connected to a
microprocessor I/O devoted to flash timing control, and the TRIG_EN bit must be set in
advance. Both triggering modes can benefit of the internal flash time counter, that uses the
TRIG_EN bit and can work either as a safety shut-down timer or as a flash duration timer.
flash mode can start only if PWR_ON=1. LED current is controlled by the value set by the
FDIM_0~3 of the DIM_REG.
t
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9.3
TCH_ON
When set from Ready mode, the STCF06 enters the torch mode. The LED current is
controlled by the value set by the TDIM_0~3 of the DIM_REG.
Doc ID 14549 Rev 3
23/35
Description of internal registers
9.4
STCF06
NTC_ON
In ready mode, the comparators that monitor the LED temperature are activated if NTC_ON
bit is set. NTC-related blocks are always active regardless of this bit in torch mode and flash
mode.
9.5
FTIM_0~3
This 4-bits register defines the maximum flash duration. It is intended to limit the energy
dissipated by the LED to a maximum safe value or to leave to the STCF06 the control of the
flash duration during normal operation. Values from 0~15 correspond to 0 ~ 1.5 s (100 ms
steps). The timing accuracy is related to the internal oscillator frequency that clocks the
flash time counter (+/- 20 %). Entering flash mode (either by soft or hard triggering) activates
the flash time counter, which begins counting down from the value loaded in the F_TIM
register. When the counter reaches zero, flash mode is stopped by resetting TRIG_EN bit,
and simultaneously the ATN pin is set to true (LOW) to alert the microprocessor that the
maximum time has been reached. FTIM value remains unaltered at the end of the count.
)
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Table 11.
r
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Dimming register
DIM_REG
(write mode)
MSB
SUB ADD=01
TDIM_3
TDIM_2
TDIM_1
Power-ON, SHUTDOWN
MODE RESET Value
0
0
0
9.6
TDIM_0~3
)
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bs
TDIM_0
-O
0
LSB
FDIM_3
FDIM_2
FDIM_1
FDIM_0
0
0
0
0
u
d
o
These 4 bits define the LED current in torch mode with 16 values fitting an exponential law.
Max torch current value is 25% of max flash current. (Figure 12)
9.7
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FDIM_0~3
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24/35
These 4 bits define the LED current in flash mode with 16 values fitting an exponential law.
The Max value of the current is set by the external resistors RFL and RTR. (Figure 12)
Doc ID 14549 Rev 3
STCF06
Description of internal registers
Figure 12. Flash and torch current vs. dimming value
1600
Torch current
Flash current
1400
ILED [mA]
1200
1000
800
600
)
s
(
ct
400
200
0
0
2
4
6
8
10
12
14
u
d
o
16
18
dimming value
Note:
LED current values refer to RFL = 0.15 Ω, RTR = 1.0 Ω
Table 12.
Auxiliary register
AUX_REG
(write mode)
MSB
SUB ADD=02
AUXI_3
Power-ON,
SHUTDOWN MODE
RESET Value
0
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AUXI_2
O
)
AUXI_1
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0
bs
0
LSB
AUXI_0
AUXT_3
AUXT_2
AUXT_1
AUXT_0
0
0
0
0
0
u
d
AUXI_0~3o
r
P
ete
9.8
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This 4 bits register defines the AUX LED current from 0 to 20 mA. See AUX LED Dimming
Table for reference. Loading any value between 1 and 15 also starts the AUX LED current
source timer, if enabled. The AUX LED current source is active only in Ready mode, and is
deactivated in any other mode.
AUXT_0~3
This 4 bit register controls the timer that defines the ON-time of the AUX LED current
source. ON-time starts when the AUXI register is loaded with any value other than zero, and
stops after the time defined in the AUXT register. Values from 1 to 14 of the AUXT register
correspond to an ON-time of the AUX LED ranging from 100 to 1400 ms in 100 ms steps.
The value 15 puts the AUX LED to the continuous light mode. The activation/deactivation of
the AUX LED current source is controlled using only the AUXI register.
Doc ID 14549 Rev 3
25/35
Description of internal registers
STCF06
Auxiliary LED dimming table (1)
Table 13.
AUXI (hex)
0
1
2
3
4
5
6
7
AUX LED
current [mA]
0.0
1.3
2.6
4.0
5.3
6.6
8.0
9.3
8
9
A
B
C
D
E
F
10.6 12.0 13.3 14.6 16.0 17.3 18.6 20.0
1. 20 mA output current is achievable only if the supply voltage is higher than 3.3 V.
Table 14.
T_DIM
(hex)
0
Torch mode and flash mode dimming registers settings
1
2
3
4
5
6
7
F_DIM
(hex)
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
LED
current
[mA]
28
34
40
48
58
69
83
98
116
139
165
197
220
266 313 373 446 526
Internal
step
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VREF1
[mV]
33
40
47
56
67
80
95
113
134
160
190
227
33
40
47
56
67
RFL RFL RFL RFL RFL RFL RFL RFL RFL RFL RFL RFL
+
+
+
+
+
+
+
+
+
+
+
+
RFL
RTR RTR RTR RTR RTR RTR RTR RTR RTR RTR RTR RTR
RFL
RFL
RFL
RFL
Sense
Resist.
15
Table 15.
Status register
d
o
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SUB ADD=03
P
e
Power-ON,
SHUTDOWN MODE
RESET Value
s
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9.10
9.11
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MSB
N/A
0
B
)
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C
du
633 753 893
o
r
P
D
E
F
1066
1266
1513
18
19
20
21
22
23
24
79
95
113 134
160
190
227
RFL
RFL
RFL
RFL
RFL
RFL
RFL
s
b
O
LED current values refer to RFL = 0.15 Ω, RTR = 1 Ω.
STAT_REG
(read mode)
17
e
t
e
ol
Note:
)
(s
16
A
LSB
F_RUN
LED_F
NTC_W
NTC_H
OT_F
N/A
VOUTOK_N
0
0
0
0
0
0
0
F_RUN
This bit is kept HIGH by the STCF06 during flash mode. By checking this bit, the
microprocessor can verify if the flash mode is running or has been terminated by the time
counter.
LED_F
This bit is set by the STCF06 when the voltage seen on the VOUT pin is VREF2 > 5.3 V
during a torch or flash operation. This condition can be caused by an open LED, indicating a
LED failure. The device automatically goes into Ready mode to avoid damage. Internal high
frequency filtering avoids false detections. This bit is reset by the STCF06 following a read
operation of the STAT_REG.
26/35
Doc ID 14549 Rev 3
STCF06
9.12
Description of internal registers
NTC_W
This bit is set HIGH by the STCF06 and the ATN pin is pulled down, when the voltage seen
on the pin RX exceeds VREF4 = 0.56 V. This threshold corresponds to a warning temperature
value at the LED measured by the NTC. The device is still operating, but a warning is sent to
the microprocessor. This bit is reset by the STCF06 following a read operation of the
STAT_REG.
9.13
NTC_H
This bit is set HIGH by the STCF06 and the ATN pin is pulled down, when the voltage seen
on the pin RX exceeds VREF5. This threshold (1.2 V) corresponds to an excess temperature
value at the LED measured by the NTC. The device is put in Ready mode to avoid damaging
the LED. This bit is reset by the STCF06 following a read operation of the STAT_REG.
9.14
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OT_F
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This bit is set HIGH by the STCF06 and the ATN pin is pulled down, when the chip overtemperature protection (~140 °C) has put the device in Ready mode. This bit is reset by the
STCF06 following a read operation of the STAT_REG.
9.15
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VOUTOK_N
)
(s
s
b
O
This bit is set by the STCF06. It is used to protect the device, if the output is shorted. The
VOUTOK_N bit is set to HIGH at the start-up. Then a current generator of 20 mA charges
the output capacitor for 360 µs typ. and it detects when the output capacitor reaches 100
mV. If this threshold is reached the bit is set to LOW. If the output is shorted to ground or the
LED is shorted, this threshold is never reached: the bit stays HIGH, ATN pin is pulled down
and the device will not start. This bit is reset following a read operation of the STAT_REG.
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Figure 13. VOUTOK_N behavior
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Doc ID 14549 Rev 3
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Description of internal registers
Table 16.
STCF06
Status register details
Bit Name
F_RUN
LED_F
(STAT_REG) (STAT_REG)
NTC_W
(STAT_REG)
NTC_H
(STAT_REG)
OT_F
(STAT_REG)
VOUTOK_N
(STAT_REG)
Default value
0
0
0
0
0
0
Latched (1)
NO
YES
YES
YES
YES
YES
Forces
Ready mode
when set
NO
YES
NO
YES
YES
YES
Sets ATN
LOW when
set
NO
YES
YES
YES
YES
YES
)
s
(
ct
1. YES means that the bit is set by internal signals and is reset to default by an I²C read operation of STAT_REG. NO means
that the bit is set and reset by internal signals in real-time.
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Doc ID 14549 Rev 3
STCF06
Typical performance characteristics
Typical performance characteristics
10
Figure 14. Efficiency vs. VBAT flash mode
Figure 15. Efficiency vs. VBAT, torch mode
90.00
90
85.00
80
Efficiency [%]
Efficiency [%]
80.00
75.00
70.00
65.00
IO = 1 A
60.00
IO = 1.5 A
55.00
VLED = 3.75 V
3
3.5
4
ILED = 30 mA
50
ILED = 165 mA
40
4.5
5
VLED = 3 V
20
2.5
5.5
3
3.5
Figure 16. Maximum output current vs. VBAT
5
5.5
o
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s
b
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1.54
1.53
1.6
1.4
1.2
1
0.8
0.6
0.4
)-
t(s
uc
d
o
r
1.52
2.5
3
3.5
P
e
4
4.5
1.51
1.5
1.49
1.48
VLED = 3.75 V
0.2
0
VBAT = 3.6 V
1.47
1.46
5
-55
5.5
-35
-15
5
25
45
65
85
TEMP [°C]
VBAT [V]
t
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bs
Figure 18. Input current vs. VBAT (VLED = 3.75
V)
3
Figure 19. Input current vs. VBAT (ILED = 1 A)
3
ILED = 1 A
ILED = 1.3 A
2.5
VLED = 3.8 V
2.5
ILED = 1.5 A
VLED = 4 V
IIN [A]
2
IIN [A]
4.5
Figure 17. Flash current vs. temperature
ILED [A]
ILED [A]
2
1.8
e
t
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ol
du
4
VBAT [V]
VBAT [V]
O
)
s
(
ct
ILED = 370 mA
30
50.00
2.5
70
60
1.5
2
1.5
1
1
0.5
ILED = 1 A
VLED = 3.75 V
0.5
0
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
VBAT [V]
VBAT [V]
Doc ID 14549 Rev 3
29/35
Typical performance characteristics
STCF06
Figure 20. ILED flash vs. FDIM
1600
1200
300
1000
250
800
600
200
150
400
100
200
50
0
RFL = 0.15 Ω
RTR = 1 Ω
350
ILED [A]
ILED [A]
400
RFL = 0.15 Ω
RTR = 1 Ω
1400
Figure 21. ILED torch vs. TDIM
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
2
3
4
FDIM
1
2
3
4
5
Flash Timeout [ms]
r
P
e
7
8
s
b
O
t
c
u
od
6
7
8
r
P
e
)
(s
0
6
9 10 11 12 13 14 15
u
d
o
t
e
l
o
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
5
TDIM
Figure 22. Flash time dimming steps
9 10 11 12 13 14 15
FTIM
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Doc ID 14549 Rev 3
STCF06
11
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
)
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Doc ID 14549 Rev 3
31/35
Package mechanical data
STCF06
TFBGA25 mechanical data
mm.
mils.
Dim.
A
Min.
Typ.
Max.
Min.
Typ.
Max.
1.0
1.1
1.16
39.4
43.3
45.7
A1
0.25
A2
0.78
b
0.25
D
2.9
9.8
0.86
30.7
0.30
0.35
9.8
11.8
3.0
3.1
114.2
118.1
D1
E
2
2.9
2
e
0.5
SE
0.25
3.1
114.2
bs
e
t
e
ol
)
s
(
ct
-O
)
s
(
ct
13.8
du
o
r
P
78.8
3.0
E1
33.9
118.1
122.0
122.0
78.8
19.7
9.8
u
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P
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7539979/A
32/35
Doc ID 14549 Rev 3
STCF06
Package mechanical data
Tape & reel TFBGA25 mechanical data
mm.
inch.
Dim.
Min.
Typ.
Max.
A
Min.
Typ.
330
Max.
13.2
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
0.504
0.519
)
s
(
ct
14.4
0.567
Ao
3.3
0.130
Bo
3.3
0.130
Ko
1.60
u
d
o
Pr
0.063
Po
3.9
4.1
P
7.9
8.1
)
(s
ete
0.153
s
b
O
ol
0.311
0.161
0.319
t
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Doc ID 14549 Rev 3
33/35
Revision history
STCF06
12
Revision history
Table 17.
Document revision history
Date
Revision
Changes
18-Mar-2008
1
First release
09-May-2008
2
Modified: packaging, Table 1 on page 1
29-Jul-2010
3
Modified Figure 2 on page 8
)
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Doc ID 14549 Rev 3
STCF06
)
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Please Read Carefully:
u
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Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
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r
P
e
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t
e
l
o
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)
(s
s
b
O
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
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c
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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
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b
O
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
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