STD10LN80K5

STD10LN80K5 N-channel 800 V, 0.55 Ω typ., 8 A MDmesh™ K5 Power MOSFET in a DPAK package Datasheet - production data Features      Order code VDS RDS(on) max. ID STD10LN80K5 800 V 0.63 Ω 8A Industry’s lowest RDS(on) x area Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Figure 1: Internal schematic diagram Applications  Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Table 1: Device summary Order code Marking Package Packing STD10LN80K5 10LN80K5 DPAK Tape and reel March 2016 DocID029039 Rev 1 This is information on a product in full production. 1/17 www.st.com Contents STD10LN80K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 9 4 Package information ..................................................................... 10 5 2/17 4.1 DPAK (TO-252) type A2 package information................................. 11 4.2 Packing information ......................................................................... 14 Revision history ............................................................................ 16 DocID029039 Rev 1 STD10LN80K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ± 30 V ID Drain current (continuous) at TC = 25 °C 8 A ID Drain current (continuous) at TC = 100 °C 5 A Drain current (pulsed) 32 A W (1) ID PTOT Total dissipation at TC = 25 °C 110 dv/dt (2) Peak diode recovery voltage slope 4.5 dv/dt (3) MOSFET dv/dt ruggedness 50 Tj Operating junction temperature range Tstg Storage temperature range - 55 to 150 V/ns °C Notes: (1) Pulse width limited by safe operating area. (2) ISD ≤ 8 A, di/dt ≤ 100 A/µs; VDS peak < V(BR)DSS, VDD=640 V (3) VDS ≤ 640 V Table 3: Thermal data Symbol Parameter Rthj-case Rthj-pcb (1) Value Unit Thermal resistance junction-case 1.14 °C/W Thermal resistance junction-pcb 50 °C/W Value Unit Notes: (1) When mounted on FR-4 board of 1 inch² , 2 oz Cu Table 4: Avalanche characteristics Symbol Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 2.7 A EAS Single pulse avalanche energy (starting Tj = 25 ° C, ID = IAR, VDD = 50 V) 240 mJ DocID029039 Rev 1 3/17 Electrical characteristics 2 STD10LN80K5 Electrical characteristics TC = 25 ° C unless otherwise specified Table 5: On/off-state Symbol Parameter V(BR)DSS Drain-source breakdown voltage Test conditions Min. VGS = 0 V, ID = 1 mA 800 Typ. Max. Unit V VGS = 0 V, VDS = 800 V 1 µA IDSS Zero gate voltage drain current VGS = 0 V, VDS = 800 V (1) TC = 125 °C 50 µA IGSS Gate body leakage current VDS = 0 V, VGS = ± 20 V ± 10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 4 5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 4 A 0.55 0.63 Ω Min. Typ. Max. Unit - 427 - pF - 43 - pF 3 Notes: (1) Defined by design, not subject to production test. Table 6: Dynamic Symbol Ciss Parameter Test conditions Input capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance - 0.25 - pF (1) Equivalent capacitance time related - 72 - pF Co(er) (2) Equivalent capacitance energy related 27 - pF Rg Intrinsic gate resistance f = 1 MHz , ID= 0 A - 7 - Ω Qg Total gate charge - 15 - nC Qgs Gate-source charge - 4.2 - nC Qgd Gate-drain charge VDD = 640 V, ID = 8 A VGS= 10 V See Figure 16: "Test circuit for gate charge behavior" - 9 - nC Co(tr) VDS = 0 to 640 V, VGS = 0 V Notes: (1) Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when V DS increases from 0 to 80% VDSS (2) Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 4/17 DocID029039 Rev 1 STD10LN80K5 Electrical characteristics Table 7: Switching times Symbol td(on) tr Parameter Test conditions tf Typ. Max. Unit - 11.8 - ns - 10 - ns - 28 - ns - 13 - ns Min. Typ. Max. Unit VDD= 400 V, ID = 4 A, RG = 4.7 Ω VGS = 10 V See Figure 15: "Test circuit for resistive load switching times" and Figure 20: "Switching time waveform" Turn-on delay time Rise time td(off) Min. Turn-off delay time Fall time Table 8: Source-drain diode Symbol ISD Parameter Test conditions Source-drain current - 8 A (1) Source-drain current (pulsed) - 32 A (2) ISDM VSD Forward on voltage ISD = 8 A, VGS = 0 V - trr Reverse recovery time ISD = 8 A, di/dt = 100 A/µs, - 350 1.5 ns V Qrr Reverse recovery charge - 3.9 µC IRRM Reverse recovery current VDD = 60 V See Figure 17: "Test circuit for inductive load switching and diode recovery times" - 22.5 A trr Reverse recovery time ISD = 8 A, di/dt = 100 A/µs, - 505 ns Qrr Reverse recovery charge - 5 µC IRRM Reverse recovery current VDD = 60 V, Tj = 150 °C See Figure 17: "Test circuit for inductive load switching and diode recovery times" - 20 A Min. Typ. Max. Unit 30 - - V Notes: (1) (2) Pulse width limited by safe operating area Pulsed: pulse duration = 300 µ s, duty cycle 1.5% Table 9: Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS= ± 1mA, ID= 0 A The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry. DocID029039 Rev 1 5/17 Electrical characteristics 2.2 6/17 STD10LN80K5 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID029039 Rev 1 STD10LN80K5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Output capacitance stored energy Figure 13: Source-drain diode forward characteristics DocID029039 Rev 1 7/17 Electrical characteristics STD10LN80K5 Figure 14: Maximum avalanche energy vs starting TJ 8/17 DocID029039 Rev 1 STD10LN80K5 3 Test circuits Test circuits Figure 15: Test circuit for resistive load switching times Figure 16: Test circuit for gate charge behavior Figure 17: Test circuit for inductive load switching and diode recovery times Figure 18: Unclamped inductive load test circuit Figure 19: Unclamped inductive waveform Figure 20: Switching time waveform DocID029039 Rev 1 9/17 Package information 4 STD10LN80K5 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. 10/17 DocID029039 Rev 1 STD10LN80K5 4.1 Package information DPAK (TO-252) type A2 package information Figure 21: DPAK (TO-252) type A2 package outline 0068772_type-A2_rev21 DocID029039 Rev 1 11/17 Package information STD10LN80K5 Table 10: DPAK (TO-252) type A2 mechanical data mm Dim. Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 5.10 5.20 5.30 e 2.16 2.28 2.40 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 L1 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 12/17 Typ. 5.10 5.25 6.60 1.00 0.20 0° DocID029039 Rev 1 8° STD10LN80K5 Package information Figure 22: DPAK (TO-252) recommended footprint (dimensions are in mm) DocID029039 Rev 1 13/17 Package information 4.2 STD10LN80K5 Packing information Figure 23: DPAK (TO-252) tape outline 14/17 DocID029039 Rev 1 STD10LN80K5 Package information Figure 24: DPAK (TO-252) reel outline Table 11: DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 B1 D 1.5 D1 1.5 E 1.65 F 1.6 Min. Max. 330 13.2 D 20.2 G 16.4 1.85 N 50 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 DocID029039 Rev 1 18.4 22.4 15/17 Revision history 5 STD10LN80K5 Revision history Table 12: Document revision history 16/17 Date Revision 09-Mar-2016 1 DocID029039 Rev 1 Changes First release. STD10LN80K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID029039 Rev 1 17/17