STD10NF30

STD10NF30 Datasheet Automotive-grade N-channel 300 V, 0.28 Ω typ., 10 A, MESH OVERLAY™ Power MOSFET in a DPAK package Features TAB 2 3 1 DPAK • • • • D(2, TAB) Order code VDS RDS(on) max. ID STD10NF30 300 V 0.33 Ω 10 A AEC-Q101 qualified 100% avalanche tested Low capacitance and gate charge 175 °C maximum junction temperature Applications G(1) • Switching applications Description S(3) AM01475v1_noZen This fully clamped MOSFET is produced using ST’s latest advanced Mesh overlay process, which is based on an innovative strip layout. The inherent benefits of the new technology coupled with the extra clamping capabilities make this product particularly suitable for the harshest operation conditions, such as those encountered in the automotive environment. The device is also well-suited for other applications where extra ruggedness is required. Product status link STD10NF30 Product summary Order code STD10NF30 Marking 10NF30 Package DPAK Packing Tape and reel DS10271 - Rev 2 - July 2018 For further information contact your local STMicroelectronics sales office. www.st.com STD10NF30 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 300 V VGS Gate-source voltage ±20 V Drain current (continuous) at TC = 25 °C 10 A Drain current (continuous) at TC = 100 °C 6.3 A IDM Drain current (pulsed) 40 A PTOT Total dissipation at TC = 25 °C 103 W Peak diode recovery voltage slope 12 V/ns -55 to 175 °C Value Unit Thermal resistance junction-case 1.45 °C/W Thermal resistance junction-pcb 50 °C/W Value Unit 6 A 175 mJ ID (1) dv/dt(2). Tstg Storage temperature range Tj Operating junction temperature range 1. Pulse width limited by safe operating area. 2. ISD ≤ 10 A, di/dt ≤ 200 A/μs, VDD= 80% V(BR)DSS Table 2. Thermal data Symbol Rthj-case (1) Rthj-pcb Parameter 1. When mounted on 1 inch² FR-4, 2 Oz copper board. Table 3. Avalanche characteristics Symbol IAR EAS DS10271 - Rev 2 Parameter Avalanche current, repetitive or non-repetitive (pulse width limited by TJmax) Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) page 2/16 STD10NF30 Electrical characteristics 2 Electrical characteristics TCASE = 25 °C unless otherwise specified. Table 4. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. 300 Zero gate voltage drain current 1 µA 10 µA ±100 nA 3 4 V 0.28 0.33 Ω Min. Typ. Max. Unit - 780 - pF - 110 - pF - 15 - pF VGS = 0 V, VDS = 300 V, TC = 125 °C(1) IGSS Gate body leakage current VDS = 0 V, VGS = ±20 V VGS(th) Gate threshold voltage VDD = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 5 A Unit V VGS = 0 V, VDS = 300 V IDSS Max. 2 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge VDD = 240 V, ID = 10 A - 23 - nC Qgs Gate-source charge VGS = 0 to 10 V - 3.5 - nC Gate-drain charge (see Figure 13. Test circuit for gate charge behavior) - 11.3 - nC Min. Typ. Max. Unit Qgd VDS = 25 V, f = 1 MHz, VGS = 0 V Table 6. Switching times Symbol td(on) tr td(off) tf Parameter Test conditions Turn-on delay time VDD = 150 V, ID = 5 A, - 13.5 - ns Rise time RG = 4.7 Ω, VGS = 10 V - 9.5 - ns Turn-off delay time (see Figure 12. Test circuit for resistive load switching times and Figure 17. Switching time waveform) - 32 - ns - 9.5 - ns Min. Typ. Max. Unit Fall time Table 7. Source-drain diode Symbol ISD ISDM(1) VSD DS10271 - Rev 2 (2) Parameter Test conditions Source-drain current - 10 A Source-drain current (pulsed) - 40 A - 1.5 V Forward on voltage ISD = 10 A, VGS = 0 V page 3/16 STD10NF30 Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit trr Reverse recovery time ISD = 10 A, di/dt = 100 A/µs, - 145 ns Qrr Reverse recovery charge VDD = 60 V - 0.76 μC Reverse recovery current (see Figure 14. Test circuit for inductive load switching and diode recovery times) - 10.3 A Reverse recovery time ISD = 10 A, di/dt = 100 A/µs, - 174 ns Reverse recovery charge VDD = 60 V, TJ = 150 °C - 1.08 μC Reverse recovery current (see Figure 14. Test circuit for inductive load switching and diode recovery times) - 12.5 A IRRM trr Qrr IRRM 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DS10271 - Rev 2 page 4/16 STD10NF30 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Thermal impedance Figure 1. Safe operating area AM18166v1 ID (A) 102 10µs 101 100µs is ea ) ar on s DS( i th R x in n ma tio y ra d b e p ite O m Li 100 10-1 10-1 1ms 10ms Tj=175 °C Tc=25 °C Single pulse 100 VDS(V) 102 101 Figure 3. Output characteristics Figure 4. Transfer characteristics AM06477v3 ID (A) VGS=10V AM06478v3 ID (A) VDS=15V 25 25 6V 7V 20 20 15 15 10 10 5V 5 5 4V 0 0 8 4 12 16 VDS(V) Figure 5. Static drain-source on-resistance 0 0 3 4 5 6 7 VGS(V) Figure 6. Gate charge vs gate-source voltage AM15981v3 RDS(on) (Ω) AM06479v3 VGS (V) VGS=10V 0.42 VDD=240V ID=10A 10 VDS 0.38 0.34 VDS (V) 250 8 200 6 150 4 100 2 50 0.3 0.26 DS10271 - Rev 2 2 6 10 14 18 ID(A) 0 0 5 10 15 20 25 0 Qg(nC) page 5/16 STD10NF30 Electrical characteristics (curves) Figure 8. Normalized gate threshold voltage vs temperature Figure 7. Capacitance variations AM06481v3 C (pF) AM06483v3 VGS(th) (norm) ID=250µA 1.1 1000 Ciss 1.0 100 0.9 Coss 0.8 10 Crss 0.7 1 0.1 1 100 10 0.6 -75 VDS(V) AM06484v3 (norm) 75 125 TJ(°C) AM15982v3 V(BR)DSS (norm) ID=5A VGS=10V 2.75 25 Figure 10. Normalized V(BR)DSS vs temperature Figure 9. Normalized on-resistance vs temperature RDS(on) -25 ID=1mA 1.1 2.25 1.05 1.75 1 1.25 0.95 0.75 0.25 -75 -25 25 75 0.9 -75 125 TJ(°C) -25 25 75 125 TJ(°C) Figure 11. Source-drain diode forward characteristics AM15720v3 VSD(V) TJ=-50°C 1 0.9 TJ=25°C 0.8 0.7 TJ=175°C 0.6 0.5 2 DS10271 - Rev 2 6 10 14 18 ISD(A) page 6/16 STD10NF30 Test circuits 3 Test circuits Figure 12. Test circuit for resistive load switching times Figure 13. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 14. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 15. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 17. Switching time waveform Figure 16. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS10271 - Rev 2 page 7/16 STD10NF30 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS10271 - Rev 2 page 8/16 STD10NF30 DPAK (TO-252) type A2 package information 4.1 DPAK (TO-252) type A2 package information Figure 18. DPAK (TO-252) type A2 package outline 0068772_type-A2_rev25 DS10271 - Rev 2 page 9/16 STD10NF30 DPAK (TO-252) type A2 package information Table 8. DPAK (TO-252) type A2 mechanical data Dim. mm Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 5.10 5.20 5.30 e 2.159 2.286 2.413 e1 4.445 4.572 4.699 H 9.35 10.10 L 1.00 1.50 L1 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 DS10271 - Rev 2 Typ. 5.10 5.25 6.60 1.00 0.20 0° 8° page 10/16 STD10NF30 DPAK (TO-252) type A2 package information Figure 19. DPAK (TO-252) recommended footprint (dimensions are in mm) FP_0068772_25 DS10271 - Rev 2 page 11/16 STD10NF30 DPAK (TO-252) packing information 4.2 DPAK (TO-252) packing information Figure 20. DPAK (TO-252) tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 K0 For machine ref. only including draft and radii concentric around B0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 DS10271 - Rev 2 page 12/16 STD10NF30 DPAK (TO-252) packing information Figure 21. DPAK (TO-252) reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 9. DPAK (TO-252) tape and reel mechanical data Tape Dim. mm mm Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 DS10271 - Rev 2 Reel Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 18.4 22.4 page 13/16 STD10NF30 Revision history Table 10. Document revision history Date Version 27-Mar-2014 1 Changes Initial release. Removed maturity status indication from cover page. The document status is production data. 02-Jul-2018 2 Updated Section 4.1 DPAK (TO-252) type A2 package information. Minor text changes. DS10271 - Rev 2 page 14/16 STD10NF30 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 DPAK (TO-252) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 DS10271 - Rev 2 page 15/16 STD10NF30 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS10271 - Rev 2 page 16/16