STD12N60M2

STD12N60M2 Datasheet N-channel 600 V, 0.395 Ω typ., 9 A MDmesh M2 Power MOSFET in a DPAK package Features TAB 2 3 1 DPAK D(2, TAB) Order code VDS RDS(on) max. ID STD12N60M2 600 V 0.450 Ω 9A • • Extremely low gate charge Excellent output capacitance (COSS) profile • • 100% avalanche tested Zener-protected Applications G(1) • Switching applications Description S(3) AM15572v1_tab This device is an N-channel Power MOSFET developed using MDmesh M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Product status STD12N60M2 Product summary Order code STD12N60M2 Marking 12N60M2 Package DPAK Packing Tape and reel DS10854 - Rev 2 - April 2019 For further information contact your local STMicroelectronics sales office. www.st.com STD12N60M2 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ± 25 V ID Drain current (continuous) at TC = 25 °C 9 A ID Drain current (continuous) at TC= 100 °C 5.7 A Drain current (pulsed) 36 A Total power dissipation at TC = 25 °C 85 W Peak diode recovery voltage slope 15 V/ns MOSFET dv/dt ruggedness 50 V/ns - 55 to 150 °C IDM (1) PTOT dv/dt (2) dv/dt (3) Tstg Tj Storage temperature range Operating junction temperature range 1. Pulse width limited by safe operating area. 2. ISD ≤ 9 A, di/dt ≤ 400 A/µs; VDS peak < V(BR)DSS, VDD = 400 V 3. VDS ≤ 480 V Table 2. Thermal data Symbol Rthj-case Parameter Thermal resistance junction-case Rthj-pcb (1) Thermal resistance junction-pcb Value Unit 1.47 °C/W 50 °C/W Value Unit 1. When mounted on FR-4 board of 1 inch², 2 oz Cu Table 3. Avalanche characteristics Symbol DS10854 - Rev 2 Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 2.6 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 117 mJ page 2/19 STD12N60M2 Electrical characteristics 2 Electrical characteristics (TC= 25 °C unless otherwise specified) Table 4. On/off states Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage IDSS Zero gate voltage Drain current IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 4.5 A Min. VGS = 0 V, ID = 1 mA Typ. 600 Unit V VGS = 0 V, VDS = 600 V VGS = 0 V, VDS = 600 V, TC = 125 Max. 1 µA 100 µA ±10 µA 3 4 V 0.395 0.450 Ω Min. Typ. Max. Unit - 538 - pF - 29 - pF - 1.1 - pF °C(1) 2 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Test conditions VDS= 100 V, f = 1 MHz, VGS = 0 V Reverse transfer capacitance (1) Equivalent output capacitance VDS = 0 V to 480 V, VGS = 0 V - 106 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 7 - Ω Qg Total gate charge - 16 - nC Qgs Gate-source charge - 2.3 - nC Qgd Gate-drain charge - 8.5 - nC Coss eq. VDD = 480 V, ID = 9 A, VGS = 0 to 10 V (see Figure 14. Test circuit for gate charge behavior) 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS Table 6. Switching times Symbol td(on) tr td(off) tf DS10854 - Rev 2 Parameter Test conditions Turn-on delay time Rise time Turn-off-delay time Fall time VDD = 300 V, ID = 4.5 A RG = 4.7 Ω, VGS = 10 V (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) Min. Typ. Max. Unit - 9.2 - ns - 9.2 - ns - 56 - ns - 18 - ns page 3/19 STD12N60M2 Electrical characteristics Table 7. Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 9 A ISDM (1) Source-drain current (pulsed) - 36 A VSD (2) Forward on voltage - 1.6 V trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr VGS = 0 V, ISD = 9 A ISD = 9 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 15. Test circuit for inductive load switching and diode recovery times) Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 9 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 284 ns - 2.4 µC - 17 A - 404 ns - 3.5 µC - 17.5 A 1. Pulse width is limited by safe operating area 2. Pulse test: pulse duration = 300 µs, duty cycle 1.5% DS10854 - Rev 2 page 4/19 STD12N60M2 Electrical characteristics curves 2.1 Characteristics curves Figure 1. Safe operating area ID (A) Figure 2. Thermal impedance 10µs D S( on 10 GC20460 K ) O p lim era ite tion d by in t m his ax a R rea is GIPD290120151436ALS 100µs 1 1ms 10ms 0.1 0.01 0.1 100 10-1 Tj = 150 °C Tc = 25 °C Single pulse 1 10 100 VDS(V) 10-2 10-5 Figure 3. Output characteristics ID (A) GIPG290120151509ALS 10-2 10-1 tp (s) GIPG290120151527ALS V DS = 11 V 12 V GS = 5 V 8 4 DS10854 - Rev 2 ID (A) 16 V GS = 6 V 12 0 0 10-3 Figure 4. Transfer characteristics V GS = 7, 8, 9, 10 V 16 10-4 V GS = 4 V 4 8 12 V DS (V) 8 4 0 0 2 4 6 8 V GS (V) page 5/19 STD12N60M2 Electrical characteristics curves Figure 5. Normalized gate threshold voltage vs temperature V (BR)DSS (norm.) AM03184v1 VGS(th) (norm) 1.10 Figure 6. Normalized V(BR)DSS vs temperature GIPG110515MQF1LBDV I D = 1 mA 1.08 1.04 1.00 ID = 250 µA 1.00 0.90 0.96 0.80 0.92 0.70 -50 0 50 Tj(°C) 100 Figure 7. Static drain-source on-resistance R DS(on) (Ω) -25 25 75 V GS = 10 V 125 T j (°C) Figure 8. Normalized on-resistance vs temperature R DS(on) (norm.) GIPG140520151538RID 0.415 0.88 -75 GIPG110515MQF1LRON V GS = 10 V 2.2 1.8 0.405 1.4 0.395 1.0 0.385 0.375 0 0.6 2 4 6 8 10 I D (A) 0.2 -75 12 (V) C (pF) 500 1000 V DS GIPG140515MQ6EDQVG V DS 10 V DD = 480 V ID=9A 8 400 25 75 125 GIPG290120151705ALS Ciss 100 300 6 200 2 DS10854 - Rev 2 Coss 10 4 0 0 T j (°C) Figure 10. Capacitance variations Figure 9. Gate charge vs. gate-source voltage V GS (V) -25 4 8 12 16 100 1 0 Q g (nC) 0.1 0.1 f = 1 MHz 1 10 Crss 100 VDS(V) page 6/19 STD12N60M2 Electrical characteristics curves Figure 11. Output capacitance stored energy EOSS (µJ) GIPG290120151706ALS 4 3 Figure 12. Source-drain diode forward characteristics VSD (V) GIPG290120151002ALS 1.1 Tj = -50 °C 1.0 Tj = 25 °C 0.9 2 Tj = 150 °C 0.8 0.7 1 0.6 0 0 DS10854 - Rev 2 100 200 300 400 500 600 VDS (V) 0.5 0 4 8 12 16 ISD (A) page 7/19 STD12N60M2 Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 16. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS10854 - Rev 2 page 8/19 STD12N60M2 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DS10854 - Rev 2 page 9/19 STD12N60M2 DPAK (TO-252) type A2 package information 4.1 DPAK (TO-252) type A2 package information Figure 19. DPAK (TO-252) type A2 package outline 0068772_type-A2_rev26 DS10854 - Rev 2 page 10/19 STD12N60M2 DPAK (TO-252) type A2 package information Table 8. DPAK (TO-252) type A2 mechanical data Dim. mm Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 5.10 5.20 5.30 e 2.159 2.286 2.413 e1 4.445 4.572 4.699 H 9.35 10.10 L 1.00 1.50 L1 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 DS10854 - Rev 2 Typ. 5.10 5.25 6.60 1.00 0.20 0° 8° page 11/19 STD12N60M2 DPAK (TO-252) type C2 package information 4.2 DPAK (TO-252) type C2 package information Figure 20. DPAK (TO-252) type C2 package outline 0068772_type-C2_rev26 DS10854 - Rev 2 page 12/19 STD12N60M2 DPAK (TO-252) type C2 package information Table 9. DPAK (TO-252) type C2 mechanical data Dim. mm Min. Typ. Max. A 2.20 2.30 2.38 A1 0.90 1.01 1.10 A2 0.00 0.10 b 0.72 0.85 b4 5.13 c 0.47 0.60 c2 0.47 0.60 D 6.00 D1 5.10 E 6.50 E1 5.20 e 2.186 2.286 2.386 H 9.80 10.10 10.40 L 1.40 1.50 1.70 L1 L2 6.20 5.60 6.60 6.70 5.50 0.90 1.25 0.51 BSC 0.60 L6 DS10854 - Rev 2 6.10 5.46 2.90 REF L3 L4 5.33 0.80 1.00 1.80 BSC θ1 5° 7° 9° θ2 5° 7° 9° V2 0° 8° page 13/19 STD12N60M2 DPAK (TO-252) type C2 package information Figure 21. DPAK (TO-252) recommended footprint (dimensions are in mm) DS10854 - Rev 2 page 14/19 STD12N60M2 DPAK (TO-252) packing information 4.3 DPAK (TO-252) packing information Figure 22. DPAK (TO-252) tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 K0 For machine ref. only including draft and radii concentric around B0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 DS10854 - Rev 2 page 15/19 STD12N60M2 DPAK (TO-252) packing information Figure 23. DPAK (TO-252) reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 10. DPAK (TO-252) tape and reel mechanical data Tape Dim. mm mm Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 DS10854 - Rev 2 Reel Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 18.4 22.4 page 16/19 STD12N60M2 Revision history Table 11. Document revision history DS10854 - Rev 2 Date Revision Changes 30-Jan-2014 1 First release. 12-Apr-2019 2 Added Section 4.2 DPAK (TO-252) type C2 package information. page 17/19 STD12N60M2 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.1 DPAK package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 DS10854 - Rev 2 page 18/19 STD12N60M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2019 STMicroelectronics – All rights reserved DS10854 - Rev 2 page 19/19