STD12N65M2

STD12N65M2 N-channel 650 V, 0.42 Ω typ., 8 A MDmesh M2 Power MOSFET in a DPAK package Datasheet - production data Features     DPAK (TO-252) Figure 1: Internal schematic diagram Order code VDS RDS(on)max. ID STD12N65M2 650 V 0.5 Ω 8A Extremely low gate charge Excellent output capacitance (COSS) profile 100% avalanche tested Zener-protected Applications  Switching applications Description This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Table 1: Device summary February 2015 Order code Marking Package Packing STD12N65M2 12N65M2 DPAK Tape and reel DocID027317 Rev 2 This is information on a product in full production. 1/16 www.st.com Contents STD12N65M2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/16 4.1 DPAK (TO-252) type A package information................................... 10 4.2 DPAK (TO-252) packing information ............................................... 13 Revision history ............................................................................ 15 DocID027317 Rev 2 STD12N65M2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter VGS Gate-source voltage Value Unit ± 25 V ID Drain current (continuous) at TC = 25 °C 8 A ID Drain current (continuous) at TC = 100 °C 5 A (1) IDM Drain current (pulsed) 32 A PTOT Total dissipation at TC = 25 °C 85 W dv/dt (2) Peak diode recovery voltage slope 15 V/ns dv/dt (3) MOSFET dv/dt ruggedness 50 V/ns - 55 to 150 °C Tstg Storage temperature Tj Operating junction temperature Notes: (1) Pulse width limited by safe operating area. (2) ISD ≤ 8 A, di/dt ≤ 400 A/µs; VDS peak < V(BR)DSS, VDD = 400 V. (3) VDS ≤ 520 V Table 3: Thermal data Symbol Rthj-case Rthj-pcb Parameter Thermal resistance junction-case max Value Unit 1.47 °C/W 50 °C/W (1) Thermal resistance junction-pcb max Notes: (1) When mounted on 1 inch² FR-4, 2 Oz copper board. Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetetive or not repetetive (pulse width limited by Tjmax) 1.6 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR; VDD = 50 V) 250 mJ DocID027317 Rev 2 3/16 Electrical characteristics 2 STD12N65M2 Electrical characteristics TC = 25 °C unless otherwise specified Table 5: On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 650 Unit V V GS= 0 V, VDS = 650 V 1 µA VGS = 0 V, VGSDS = 650 V TC = 125 °C 100 µA ±10 µA 3 4 V 0.42 0.5 Ω Min. Typ. Max. Unit - 535 - pF - 25 - pF - 1.1 - pF IDSS Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 4 A 2 Table 6: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Test conditions VGS = 0 V, VDS= 100 V, f = 1 MHz Equivalent output capacitance VGS = 0 V, VDS = 0 to 520 V - 144 - pF RG Intrinsic gate resistance f = 1 MHz, open drain - 7 - Ω Qg Total gate charge - 16.5 - nC Qgs Gate-source charge - 2.6 - nC Qgd Gate-drain charge - 8.5 - nC Coss eq. (1) VDD = 520 V, ID = 8 A, VGS = 10 V (see Figure 15: "Gate charge test circuit") Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDSS 4/16 DocID027317 Rev 2 STD12N65M2 Electrical characteristics Table 7: Switching times Symbol td(on) Parameter Turn-on delay time tr Rise time td(off) Turn-offdelay time tf Test conditions VDD = 325 V, ID = 4 A, RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Switching times test circuit for resistive load" and Figure 19: "Switching time waveform") Fall time Min. Typ. Max. Unit - 9 - ns - 7 - ns - 34 - ns - 13.5 - ns Min. Typ. Max. Unit Table 8: Source drain diode Symbol ISD (1) ISDM VSD (2) Parameter Test conditions Source-drain current - 8 A Source-drain current (pulsed) - 32 A - 1.6 V Forward on voltage trr Reverse recovery time Qrr Reverse recovery charge IRRM VGS = 0 V, ISD = 8 A - 313 ns - 2.7 µC Reverse recovery current - 17 A trr Reverse recovery time - 462 ns Qrr Reverse recovery charge - 4.1 µC IRRM Reverse recovery current - 17.5 A ISD = 8 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: " Test circuit for inductive load switching and diode recovery times") ISD = 8 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: " Test circuit for inductive load switching and diode recovery times") Notes: (1) (2) Pulse width is limited by safe operating area Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID027317 Rev 2 5/16 Electrical characteristics 2.1 STD12N65M2 Electrical characteristics (curves) Figure 2: Safe operating area S( on ) is 10µs O p Li era m ti ite on d by in t m his ax ar R ea D 10 Figure 3: Thermal impedance GIPD161220141753M T ID (A) 1 100µs 1ms 10ms 0.1 Tj=150°C Tc=25°C Single pulse 0.01 0.1 10 1 VDS(V) 100 Figure 4: Output characteristics ID (A) GIPD161220141803MT V GS= 7, 8, 9, 10 V Figure 5: Transfer characteristics GIPD161220141809MT ID (A) 6V 16 16 5V 12 8 8 4 0 0 4V 5 10 15 20 25 V DS(V) Figure 6: Normalized gate threshold voltage vs temperature 6/16 V DS = 18 V 12 DocID027317 Rev 2 4 0 0 2 4 6 8 V GS(V) Figure 7: Normalized V (BR)DSS vs. temperature STD12N65M2 Electrical characteristics Figure 8: Static drain-source on-resistance GIPD161220141813MT R DS(on) (Ω) Figure 9: Normalized on-resistance vs temperature V GS= 10V 0.44 0.43 0.42 0.41 0.40 0 2 4 6 8 ID(A) Figure 10: Gate charge vs. gate-source voltage GIPD161220141820MT V DS (V) V GS (V) V DS V DD = 520 V ID = 8 A 12 500 Figure 11: Capacitance variations GIPD161220141823MT C (pF) Ciss 1000 10 400 100 Coss 8 300 10 6 200 4 Crss 1 100 2 0 0 4 8 12 16 0 Q g(nC) Figure 12: Turn-off switching loss vs drain current GIPD171220141020MT E (µJ) 0.1 0.1 1 10 100 V DS(V) Figure 13: Source-drain diode forward characteristic GIPD161220141847MT V SD (V) 1.1 T j= -50°C 4 1 3 0.9 T j= 25°C 0.8 2 T j= 150°C 0.7 1 0.6 0 0 100 200 300 400 500 600 0.5 V DS(V) DocID027317 Rev 2 0 2 4 6 8 ISD(A) 7/16 Test circuits 3 STD12N65M2 Test circuits Figure 14: Switching times test circuit for resistive load Figure 15: Gate charge test circuit VDD 47 k Ω 12 V 1 kΩ 100 nF I G = CONST Vi ≤ V GS 100 Ω D.U.T. VG 2.7 k Ω 2200 μ F 47 k Ω PW 1 kΩ AM01469v 1 Figure 16: Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE B B Figure 17: Unclamped inductive load test circuit A D G S L=100 µH 3.3 µF B 25 Ω 1000 µF D G RG VDD D.U.T. S AM01470v1 Figure 19: Switching time waveform Figure 18: Unclamped inductive waveform t on V(BR)DSS t d(on) t off tr t d(off) tf VD 90% 90% I DM 10% 0 ID VDD VDD AM01472v 1 8/16 10% DocID027317 Rev 2 VGS 0 10% VDS 90% AM01473v 1 STD12N65M2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. DocID027317 Rev 2 9/16 Package information 4.1 STD12N65M2 DPAK (TO-252) type A package information Figure 20: DPAK (TO-252) type A package outline 0068772_R 10/16 DocID027317 Rev 2 STD12N65M2 Package information Table 9: DPAK (TO-252) type A mechanical data mm Dim. Min. Typ. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 E 5.10 6.40 E1 6.60 4.70 e 2.28 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 L1 2.80 L2 0.80 L4 0.60 R V2 1.00 0.20 0° DocID027317 Rev 2 8° 11/16 Package information STD12N65M2 Figure 21: DPAK (TO-252) type A recommended footprint FP0068772_R All dimensions are in mm 12/16 DocID027317 Rev 2 STD12N65M2 4.2 Package information DPAK (TO-252) packing information Figure 22: Tape for DPAK (TO-252) DocID027317 Rev 2 13/16 Package information STD12N65M2 Figure 23: Reel for DPAK (TO-252) Table 10: DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Min. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 14/16 Max. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 DocID027317 Rev 2 18.4 22.4 STD12N65M2 5 Revision history Revision history Table 11: Document revision history Date Revision 16-Dec-2014 1 First release. 2 Updated features in cover page. Updated Table 4: "Avalanche characteristics", Table 7: "Switching times", Figure 2: "Safe operating area" and Section 5.1: "DPAK (TO252) type A package information". Minor text changes. 12-Feb-2015 Changes DocID027317 Rev 2 15/16 STD12N65M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 16/16 DocID027317 Rev 2