STD13N65M2

STD13N65M2 N-channel 650 V, 0.37 Ω typ., 10 A MDmesh M2 Power MOSFET in a DPAK package Datasheet − production data Features TAB 2 Order code VDS RDS(on) max ID STD13N65M2 650 V 0.43 Ω 10 A • Extremely low gate charge 3 • Excellent output capacitance (Coss) profile 1 • 100% avalanche tested • Zener-protected DPAK Applications • Switching applications Figure 1. Internal schematic diagram , TAB Description This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. AM15572v1 Table 1. Device summary Order codes Marking Package Packaging STD13N65M2 13N65M2 DPAK Tape and reel December 2014 This is information on a product in full production. DocID027324 Rev 1 1/16 www.st.com Contents STD13N65M2 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/16 .............................................. 8 DocID027324 Rev 1 STD13N65M2 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ± 25 V ID Drain current (continuous) at TC = 25 °C 10 A ID Drain current (continuous) at TC = 100 °C 6.3 A IDM (1) Drain current (pulsed) 40 A PTOT Total dissipation at TC = 25 °C 110 W dv/dt (2) Peak diode recovery voltage slope 15 V/ns dv/dt (3) MOSFET dv/dt ruggedness 50 V/ns Tstg Tj Storage temperature - 55 to 150 °C Max. operating junction temperature 150 1. Pulse width limited by safe operating area. 2. ISD ≤ 10 A, di/dt ≤ 400 A/µs; VDS peak < V(BR)DSS, VDD=400 V. 3. VDS ≤ 520 V Table 3. Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case max 1.14 °C/W Rthj-pcb Thermal resistance junction-pcb max(1) 50 °C/W Value Unit 1. When mounted on 1 inch² FR-4, 2 Oz copper board Table 4. Avalanche characteristics Symbol Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 1.8 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR; VDD = 50 V) 350 mJ DocID027324 Rev 1 3/16 16 Electrical characteristics 2 STD13N65M2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 5. On /off states Symbol V(BR)DSS Parameter Drain-source breakdown voltage IDSS Zero gate voltage drain current IGSS Gate-body leakage current Test conditions VGS = 0 V, ID = 1 mA Min. Typ. Max. Unit 650 V VGS = 0 V, VDS = 650 V 1 µA VGS = 0 V, VDS = 650 V, TC=125 °C 100 µA VDS = 0 V, VGS = ± 25 V ±10 µA 3 4 V 0.37 0.43 Ω Min. Typ. Max. Unit - 590 - pF - 27.5 - pF - 1.1 - pF VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance 2 VGS = 10 V, ID = 5 A Table 6. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VGS = 0 V, VDS = 0 to 520 V - 168.5 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 6.5 - Ω Qg Total gate charge - 17 - nC - 3.3 - nC - 7 - nC Qgs Gate-source charge Qgd Gate-drain charge VGS = 0 V, VDS = 100 V, f = 1 MHz VDD = 520 V, ID = 10 A, VGS = 10 V (see Figure 15) 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 4/16 DocID027324 Rev 1 STD13N65M2 Electrical characteristics Table 7. Switching times Symbol td(on) tr Parameter Test conditions tf Typ. Max. Unit - 11 - ns - 7.8 - ns - 38 - ns - 12 - ns Turn-on delay time VDD = 325 V, ID = 5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 14 and 19) Rise time td(off) Min. Turn-off delay time Fall time Table 8. Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 10 A ISDM (1) Source-drain current (pulsed) - 40 A VSD (2) Forward on voltage - 1.6 V ISD trr VGS = 0 V, ISD = 10 A Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 10 A, di/dt = 100 A/µs VDD = 60 V (see Figure 16) ISD = 10 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C (see Figure 16) - 312 ns - 2.7 µC - 17.5 A - 464 ns - 4.1 µC - 17.5 A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID027324 Rev 1 5/16 16 Electrical characteristics 2.1 STD13N65M2 Electrical characteristics (curves) Figure 2. Safe operating area ,' $ Figure 3. Thermal impedance *,3'$/6 *& . —V  į  Q 2S /LP HUDW LWH LRQ G LQ E\ WK P LV D[ DUH 5 D LV '6 R     —V PV 7M ƒ& 7& ƒ& 6LQJOHSXOVH      9'69 *,3*$/6 9*6 9  =WK . 5 WK-F į W SϨ    6LQJOHSXOVH PV Figure 4. Output characteristics ,' $         WS   Ϩ  WSV Figure 5. Transfer characteristics ,' $  *,3*$/6  9'6 9 9         9     9'69 Figure 6. Normalized gate threshold voltage vs. temperature 9*6WK *,3')65     9*69 *,3')65  ,' P$          9%5'66 QRUP ,' —$  Figure 7. Normalized V(BR)DSS vs. temperature QRUP  6/16       7-ƒ&   DocID027324 Rev 1     7-ƒ& STD13N65M2 Electrical characteristics Figure 8. Static drain-source on-resistance 5'6RQ *,3')65 ȍ *,3')65 5'6RQ QRUP 9*6 9  Figure 9. Normalized on-resistance vs. temperature    9*6 9            ,'$  Figure 10. Gate charge vs. gate-source voltage 9*6 9  *,3*$/6 9'6 9  9'6     7-ƒ&  Figure 11. Capacitance variations *,3*$/6 & S)  &LVV  9'' 9 ,' $            &RVV          4JQ& Figure 12. Output capacitance stored energy (266 —- *,3*$/6 &UVV    9'69   Figure 13. Source-drain diode forward characteristics 96' 9 *,3*$/6 7- ƒ&    7- ƒ&   7- ƒ&            9'69   DocID027324 Rev 1       ,6'$ 7/16 16 Test circuits 3 STD13N65M2 Test circuits Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit 9'' 9 μF VDD VD VGS ,* &2167 9L 9 9*0$; RG Nȍ Q) 3.3 μF 2200 RL Nȍ  —) D.U.T. ȍ '87 Nȍ 9* PW Nȍ Nȍ 3: $0Y AM01468v1 Figure 16. Test circuit for inductive load switching and diode recovery times A A Figure 17. Unclamped inductive load test circuit L A D G D.U.T. FAST DIODE B B S VD L=100μH 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform 9%5'66 WRQ 9' WGRQ WRII WU WGRII   ,'0  9'' $0Y 8/16   ,' 9'' WI 9*6  DocID027324 Rev 1  9'6  $0Y STD13N65M2 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID027324 Rev 1 9/16 16 Package mechanical data STD13N65M2 Figure 20. DPAK (TO-252) type A drawing B5 10/16 DocID027324 Rev 1 STD13N65M2 Package mechanical data Table 9. DPAK (TO-252) type A mechanical data mm Dim. Min. Typ. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 E 5.10 6.40 6.60 E1 4.70 e 2.28 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 L1 2.80 L2 0.80 L4 0.60 1.00 R V2 0.20 0° 8° DocID027324 Rev 1 11/16 16 Package mechanical data STD13N65M2 Figure 21. DPAK (TO-252) footprint (a) )3B5 a. All dimensions are in millimeters 12/16 DocID027324 Rev 1 STD13N65M2 5 Packaging mechanical data Packaging mechanical data Figure 22. TapeTape for DPAK (TO-252) SLWFKHVFXPXODWLYH WROHUDQFHRQWDSHPP 7 3 7RSFRYHU WDSH 3 ' ( ) % . )RUPDFKLQHUHIRQO\ LQFOXGLQJGUDIWDQG UDGLLFRQFHQWULFDURXQG% : % $ 3 ' 8VHUGLUHFWLRQRIIHHG 5 %HQGLQJUDGLXV 8VHUGLUHFWLRQRIIHHG $0Y DocID027324 Rev 1 13/16 16 Packaging mechanical data STD13N65M2 Figure 23. Reel for DPAK (TO-252) 7 5(( /',0(16,216 PPPLQ $FFHVVKROH $WVO RWORFDWLRQ % ' & 1 $ )XOOUDGLXV *PHDVXUHGDWKXE 7DSHVORW LQFRUHIRU WDSHVWDUWPPPLQ ZLGWK $0Y Table 10. DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 Min. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 DocID027324 Rev 1 18.4 22.4 Figure 24. Revision history 14/16 Max. STD13N65M2 Packaging mechanical data Table 11. Document revision history Date Revision 18-Dec-2014 1 Changes First release. DocID027324 Rev 1 15/16 16 STD13N65M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved 16/16 DocID027324 Rev 1