STD16N65M5

STD16N65M5 Datasheet N-channel 650 V, 0.230 Ω typ., 12 A MDmesh™ M5 Power MOSFET in a DPAK package Features TAB 2 3 1 DPAK D(2, TAB) Order codes VDS at Tjmax. RDS(on) max. ID STD16N65M5 710 V 0.279 Ω 12 A • Extremely low RDS(on) • • • Low gate charge and input capacitance Excellent switching performance 100% avalanche tested Applications • G(1) Switching applications Description S(3) AM01475v1_noZen This device is an N-channel Power MOSFET based on the MDmesh™ M5 innovative vertical process technology combined with the well-known PowerMESH™ horizontal layout. The resulting product offers extremely low on-resistance, making it particularly suitable for applications requiring high power and superior efficiency. Product status link STD16N65M5 Product summary Order code STD16N65M5 Marking 16N65M5 Package DPAK Packing Tape and reel DS7011 - Rev 3 - November 2018 For further information contact your local STMicroelectronics sales office. www.st.com STD16N65M5 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Gate-source voltage ±25 V ID Drain current (continuous) at TC = 25 °C 12 A ID Drain current (continuous) at TC = 100 °C 7.3 A IDM (1) Drain current (pulsed) 48 A PTOT Total power dissipation at TC = 25 °C 90 W Peak diode recovery voltage slope 15 V/ns -55 to 150 °C Value Unit VGS dv/dt (2) Tj Tstg Parameter Operating junction temperature range Storage temperature range 1. Pulse width limited by safe operating area. 2. ISD ≤ 12 A, di/dt ≤ 400 A/μs, VDD = 400 V, VDS(peak) < V(BR)DSS. Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 1.38 °C/W Rthj-pcb (1) Thermal resistance junction-pcb 50 °C/W Value Unit 4 A 200 mJ 1. When mounted on 1inch² FR-4 board, 2 oz Cu. Table 3. Avalanche characteristics Symbol DS7011 - Rev 3 Parameter IAR Avalanche current, repetitive or not-repetitive (pulse width limited by Tj Max) EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) page 2/19 STD16N65M5 Electrical characteristics 2 Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 4. On/off states Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions ID = 1 mA, VGS = 0 V Min. Typ. Max. 650 Unit V VGS = 0 V, VDS = 650 V, 1 µA VGS = 0 V, VDS = 650 V, TC = 125 °C (1) 100 µA Gate body leakage current VDS = 0 V, VGS = ±25 V 100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 4 5 V RDS(on) Static drain-source on resistance VGS = 10 V, ID = 6 A 0.230 0.279 Ω Typ. Max. Unit - pF IDSS Zero gate voltage drain current IGSS 3 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr) (1) Co(er) (2) Equivalent capacitance time related Equivalent capacitance energy related Test conditions Min. 1250 VDS = 100 V, f = 1 MHz, VGS = 0 V - 30 3 - 100 - pF - 30 - pF - 2 - Ω - nC VDS = 0 to 520 V, VGS = 0 V Rg Gate input resistance f = 1 MHz open drain Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VDD = 520 V, ID = 12 A, VGS = 0 to 10 V (see Figure 15. Test circuit for gate charge behavior) 31 - 8 12 1. Co(tr) time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 2. Co(er) energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS. DS7011 - Rev 3 page 3/19 STD16N65M5 Electrical characteristics Table 6. Switching times Symbol Parameter Test conditions Min. Typ. td(v) Voltage delay time VDD = 400 V, ID = 8 A, 25 tr(v) Voltage rise time RG = 4.7 Ω, VGS = 10 V 7 Current fall time (see Figure 16. Test circuit for inductive load switching and diode recovery times and Figure 19. Switching time waveform) tf(i) tc(off) Crossing time - 6 Max. Unit - ns Max. Unit 8 Table 7. Source drain diode Symbol ISD Parameter Test conditions Min. Typ. Source-drain current 12 - ISDM (1) Source-drain current (pulsed) VSD (2) Forward on voltage ISD = 12 A, VGS = 0 V trr Reverse recovery time ISD = 12 A, di/dt = 100 A/µs Qrr Reverse recovery charge IRRM Reverse recovery current VDD = 100 V (see Figure 16. Test circuit for inductive load switching and diode recovery times) trr Reverse recovery time ISD = 12 A, di/dt = 100 A/µs Qrr Reverse recovery charge IRRM Reverse recovery current VDD = 100 V (see Figure 16. Test circuit for inductive load switching and diode recovery times) 48 - - - 1.5 A V 300 ns 3.5 µC 23 A 350 ns 4 µC 24 A 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 μs, duty cycle 1.5%. DS7011 - Rev 3 page 4/19 STD16N65M5 Electrical characteristics curves 2.1 Electrical characteristics curves Figure 1. Safe operating area Figure 2. Thermal impedance AM08609v1 ID (A) GC20460 K ) is 10µs D S( on O Li p e r m at ite io d ni by n m th is ax a R re a 10 1 100 100µs 1ms 10ms 10-1 0.1 Tj=150°C Tc=25°C S ingle puls e 0.01 0.1 10 1 VDS (V) 100 10-2 10-5 Figure 3. Output characterisics ID (A) AM03178v1 VGS =10V 10-4 10-3 10-2 tp (s) 10-1 Figure 4. Transfer characteristics AM03179v1 ID (A) VDS =10V 7.5V 20 20 7V 15 15 6.5V 10 10 6V 5 5 5.5V 0 0 2 4 6 8 10 12 14 16 18 VDS (V) Figure 5. Normalized V(BR)DSS vs temperature AM03187v1 V(BR)DSS (norm) ID=1mA 0 1.05 0.240 1.03 0.235 1.01 0.230 0.99 0.225 0.97 0.220 0.95 0.215 DS7011 - Rev 3 0.210 25 50 75 100 TJ (°C) VGS (V) AM03181v1 R DS (on) (Ω) 0.245 0 9 8 7 6 Figure 6. Static drain-source on resistance 1.07 0.93 -50 -25 5 4 3 0 VGS =10V 2 4 6 8 10 12 ID(A) page 5/19 STD16N65M5 Electrical characteristics curves Figure 8. Capacitance variations Figure 7. Output capacitance stored energy AM03312v1 E os s (µJ ) 7 AM03183v1 C (pF) 6 10000 5 Cis s 1000 4 3 100 2 Cos s 10 1 Crs s 0 0 100 200 300 400 500 600 Figure 9. Gate charge vs gate-source voltage AM03182v1 VGS 1 0.1 VDS (V) 1 100 10 VDS (V) Figure 10. Normalized on resistance vs temperature AM03185v1 R DS (on) (norm) VGS =10V 2.1 VDD=520V ID 1.9 10 1.7 8 1.5 3 6 200 4 1.3 1.1 0.9 100 2 0 0 25 10 30 35 Q g Figure 11. Normalized gate threshold voltage vs temperature AM03184v1 VGS (th) (norm) ID=250µA 1.10 0.7 0.5 -50 0 50 TJ (°C) 100 Figure 12. Source-drain diode forward characteristics AM03186v1 VS D (V) 1.0 TJ =-25°C 0.9 1.00 0.8 TJ =25°C 0.7 0.90 TJ =150°C 0.6 0.80 0.70 -50 DS7011 - Rev 3 0.5 0.4 0 50 100 TJ (°C) 0 5 10 IS D(A) page 6/19 STD16N65M5 Electrical characteristics curves Figure 13. Switching energy vs gate resistance AM10359v1 E (µJ ) 100 Eon 80 60 Eoff 40 20 0 0 10 20 30 40 R G (Ω) # Eon including reverse recovery of a SiC diode. DS7011 - Rev 3 page 7/19 STD16N65M5 Test circuits 3 Test circuits Figure 14. Test circuit for resistive load switching times Figure 15. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 16. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A B L A B 3.3 µF D G + VD 100 µH fast diode B Figure 17. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 18. Unclamped inductive waveform V(BR)DSS Figure 19. Switching time waveform Concept waveform for Inductive Load Turn-off Id VD 90%Vds 90%Id Tdelay -off IDM Vgs 90%Vgs on ID Vgs(I(t )) VDD VDD 10%Vds 10%Id Vds Trise AM01472v1 DS7011 - Rev 3 Tfall Tcross --over AM05540v2 page 8/19 STD16N65M5 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS7011 - Rev 3 page 9/19 STD16N65M5 DPAK (TO-252) type A2 package information 4.1 DPAK (TO-252) type A2 package information Figure 20. DPAK (TO-252) type A2 package outline 0068772_type-A2_rev25 DS7011 - Rev 3 page 10/19 STD16N65M5 DPAK (TO-252) type A2 package information Table 8. DPAK (TO-252) type A2 mechanical data Dim. mm Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 5.10 5.20 5.30 e 2.159 2.286 2.413 e1 4.445 4.572 4.699 H 9.35 10.10 L 1.00 1.50 L1 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 DS7011 - Rev 3 Typ. 5.10 5.25 6.60 1.00 0.20 0° 8° page 11/19 STD16N65M5 DPAK (TO-252) type C2 package information 4.2 DPAK (TO-252) type C2 package information Figure 21. DPAK (TO-252) type C2 package outline 0068772_C2_25 DS7011 - Rev 3 page 12/19 STD16N65M5 DPAK (TO-252) type C2 package information Table 9. DPAK (TO-252) type C2 mechanical data Dim. mm Min. Typ. Max. A 2.20 2.30 2.38 A1 0.90 1.01 1.10 A2 0.00 0.10 b 0.72 0.85 b4 5.13 c 0.47 0.60 c2 0.47 0.60 D 6.00 D1 5.10 E 6.50 E1 5.20 e 2.186 2.286 2.386 H 9.80 10.10 10.40 L 1.40 1.50 1.70 L1 L2 6.20 5.60 6.60 6.70 5.50 0.90 1.25 0.51 BSC 0.60 L6 DS7011 - Rev 3 6.10 5.46 2.90 REF L3 L4 5.33 0.80 1.00 1.80 BSC θ1 5° 7° 9° θ2 5° 7° 9° V2 0° 8° page 13/19 STD16N65M5 DPAK (TO-252) type C2 package information Figure 22. DPAK (TO-252) recommended footprint (dimensions are in mm) FP_0068772_25 DS7011 - Rev 3 page 14/19 STD16N65M5 DPAK (TO-252) packing information 4.3 DPAK (TO-252) packing information Figure 23. DPAK (TO-252) tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 K0 For machine ref. only including draft and radii concentric around B0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 DS7011 - Rev 3 page 15/19 STD16N65M5 DPAK (TO-252) packing information Figure 24. DPAK (TO-252) reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 10. DPAK (TO-252) tape and reel mechanical data Tape Dim. mm mm Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 DS7011 - Rev 3 Reel Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 18.4 22.4 page 16/19 STD16N65M5 Revision history Table 11. Document revision history Date Version 09-Nov-2010 1 Changes First release. Modified Section 2.1: Electrical characteristics (curves): – Figure 6, Figure 7, Figure 8, Figure 9, Figure 13 and Figure 14 – Added Figure 15 14-Oct-2011 2 Updated RDS(on) value in coverpage and in Table 4 Updated values in Table 6 Updated Section 4: Package mechanical data and Section 5: Packaging mechanical data. Minor text changes. Removed maturity status indication from cover page. The document status is production data. 20-Nov-2018 3 The part number STB16N65M5 has been moved to a separate datasheet. Updated Section 4 Package information. Minor text changes. DS7011 - Rev 3 page 17/19 STD16N65M5 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 DPAK (TO-252) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 DPAK (TO-252) type C2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 DS7011 - Rev 3 page 18/19 STD16N65M5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS7011 - Rev 3 page 19/19