STD1HNC60T4

STD1HNC60 N-CHANNEL 600V - 4Ω - 2A - IPAK/DPAK PowerMesh™II MOSFET TYPE STD1HNC60 ■ ■ ■ ■ ■ VDSS RDS(on) ID 600 V ID(on) x RDS(on)max, VGS = 10V Test Conditions VDS > ID(on) x RDS(on)max, ID = 1A VDS = 25V, f = 1 MHz, VGS = 0 ) s t( µA d o r 50 µA ±100 nA Min. Typ. Max. Unit 2 3 4 V 4 5 Ω P e let so Test Conditions Unit V VDS = Max Rating, TC = 125 °C Parameter Max. 1 ON (1) Symbol Typ. 600 2 Min. A Typ. Max. Unit 2 S 228 pF 40 pF 6 pF STD1HNC60 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time VDD = 300V, ID = 1 A RG = 4.7Ω VGS = 10V (see test circuit, Figure 3) 9 8.5 Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 480V, ID = 2 A, VGS = 10V 11.3 2.8 5 15.5 nC nC nC Typ. Max. Unit ns ns SWITCHING OFF Symbol tr(Voff) tf tc Parameter Test Conditions Min. VDD = 480V, ID = 2 A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 5) Off-voltage Rise Time Fall Time Cross-over Time 18 9 27 ns ns ns Max. Unit 2 ) s t( A 8 A SOURCE DRAIN DIODE Symbol ISD ISDM (2) VSD (1) Parameter Test Conditions Min. Typ. c u d Source-drain Current Source-drain Current (pulsed) Forward On Voltage ISD = 2 A, VGS = 0 trr Reverse Recovery Time Qrr Reverse Recovery Charge ISD = 2A, di/dt = 100A/µs, VDD = 100V, Tj = 150°C (see test circuit, Figure 5) IRRM Reverse Recovery Current Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. ) s ( ct Safe Operating Area e t le so o r P 1.6 V 480 ns 1032 nC 4.3 A b O - Thermal Impedence u d o r P e t e l o s b O 3/9 STD1HNC60 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance c u d e t le ) s ( ct u d o r P e Gate Charge vs Gate-source Voltage t e l o s b O 4/9 o r P o s b O - Capacitance Variations ) s t( STD1HNC60 Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature c u d Source-drain Diode Forward Characteristics e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 5/9 STD1HNC60 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit c u d e t le ) s ( ct u d o o s b O - Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times r P e t e l o s b O 6/9 o r P ) s t( STD1HNC60 TO-252 (DPAK) MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 2.20 2.40 0.087 0.094 A1 0.90 1.10 0.035 0.043 A2 0.03 0.23 0.001 0.009 B 0.64 0.90 0.025 0.035 B2 5.20 5.40 0.204 0.213 C 0.45 0.60 0.018 0.024 C2 0.48 0.60 0.019 0.024 D 6.00 6.20 0.236 0.244 E 6.40 6.60 0.252 G 4.40 4.60 0.173 H 9.35 10.10 0.368 L2 L4 V2 0.60 0 8 ) s ( ct od 0.181 0.398 0.031 1.00 o 0.260 r P e t le 0.8 uc ) s t( 0.024 o 0 o 0.039 0o o s b O - u d o r P e t e l o s b O P032P_B 7/9 STD1HNC60 TO-251 (IPAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. 2.4 0.086 MAX. 0.094 0.043 A 2.2 A1 0.9 1.1 0.035 A3 0.7 1.3 0.027 0.051 B 0.64 0.9 0.025 0.031 B2 5.2 5.4 0.204 0.212 B3 0.85 B5 0.033 0.3 0.012 B6 0.95 0.037 ) s t( C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 E 6.4 6.6 0.252 G 4.4 4.6 0.173 H 15.9 16.3 0.626 L 9 9.4 0.354 L1 0.8 1.2 0.031 L2 0.8 e t le 1 o s b O - uc 0.244 Pr od 0.260 0.181 0.641 0.370 0.047 0.031 0.039 A3 L = G 1 = 2 = 3 B B3 D = = B2 = s b O E t e l o L2 B5 r P e A1 C2 u d o B6 A ) s ( ct C H L1 0068771-E 8/9 STD1HNC60 c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics s b O © 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 9/9