STD1NK60-1

STD1NK60-1 N-channel 600 V, 7.3 Ω typ., 1 A SuperMESH™ Power MOSFET in an IPAK package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STD1NK60-1 600 V 8.5 Ω 1A 30 W TAB 2     3 1 Extremely high dv/dt capability ESD improved capability 100% avalanche tested Gate charge minimized IPAK Applications Figure 1: Internal schematic diagram    Low power battery chargers Swith mode low power supplies (SMPS) Low power, ballast, CFL (compact fluorescent lamps) D(2, TAB) Description This high voltage device is an N-channel Power MOSFET developed using the SuperMESH™ technology by STMicroelectronics, an optimization of the well-established PowerMESH™. In addition to a significant reduction in on-resistance, this device is designed to ensure a high level of dv/dt capability for the most demanding applications. G(1) S(3) AM01475v1_noZen Table 1: Device summary Order code Marking Package Packing STD1NK60-1 D1NK60 IPAK Tube February 2017 DocID030308 Rev 1 This is information on a product in full production. 1/15 www.st.com Contents STD1NK60-1 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 9 4 Package information ..................................................................... 10 5 2/15 4.1 IPAK (TO-251) type A package information .................................... 10 4.2 IPAK (TO-251) type C package information .................................... 12 Revision history ............................................................................ 14 DocID030308 Rev 1 STD1NK60-1 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 600 V VDGR Drain-gate voltage (RGS = 20 kΩ) 600 V VGS Gate-source voltage ±30 V ID Drain current (continuous) at TC = 25 °C 1.0 A ID Drain current (continuous) at TC = 100 °C 0.63 A IDM(1) Drain current (pulsed) 4 A PTOT Total dissipation at TC = 25 °C 30 W IAR Avalanche current, repetitive or not-repetitive (pulse width limited by Tjmax) 1 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 25 mJ Peak diode recovery voltage slope 3 V/ns - 55 to 150 °C Value Unit dv/dt (2) Tj Operating junction temperature range Tstg Storage temperature range Notes: (1)Pulse (2)I SD width limited by safe operating area. ≤ 1.0 A, di/dt ≤ 100 A/µs; VDD ≤ V(BR)DSS, TJ ≤ TJMAX Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 4.2 °C/W Rthj-amb Thermal resistance junction-ambient 100 °C/W DocID030308 Rev 1 3/15 Electrical characteristics 2 STD1NK60-1 Electrical characteristics TC = 25 ° C unless otherwise specified Table 4: On/off-state Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0 V, VDS = 600 V 1 µA VGS = 0 V, VDS = 600 V TC = 125 °C (1) 50 µA ±100 nA 3 3.7 V 7.3 8.5 Ω Typ. Max. Unit IDSS Zero gate voltage drain current IGSS Gate body leakage current VDS=0 V, VGS= ±30 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 0.5 A 2.25 Notes: (1)Defined by design, not subject to production test. Table 5: Dynamic Symbol Parameter Test conditions Min. Ciss Input capacitance - 156 - pF Coss Output capacitance - 23.5 - pF Crss Reverse transfer capacitance - 3.8 - pF Qg Total gate charge - 7 - nC Qgs Gate-source charge - 1.1 - nC Qgd Gate-drain charge - 3.7 - nC Test conditions Min. Typ. Max. Unit VDD= 300 V, ID = 0.5 A, RG = 4.7 Ω VGS = 10 V (see Figure 15: "Test circuit for resistive load switching times" and Figure 20: "Switching time waveform") - 6.5 - ns - 5 - ns - 19 - ns - 25 - ns VDS = 25 V, f = 1 MHz, VGS = 0 V VDD = 480 V, ID = 1 A VGS= 0 to 10 V (see Figure 16: "Test circuit for gate charge behavior") Table 6: Switching times Symbol td(on) tr td(off) tf 4/15 Parameter Turn-on delay time Rise time Turn-off delay time Fall time DocID030308 Rev 1 STD1NK60-1 Electrical characteristics Table 7: Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 1 A ISDM(1) Source-drain current (pulsed) - 4 A VSD(2) Forward on voltage ISD = 1.0 A, VGS = 0 V - 1.6 V trr Reverse recovery time - 140 ns Qrr Reverse recovery charge - 240 nC IRRM Reverse recovery current ISD = 1.0 A, di/dt = 100 A/µs, VDD = 25 V (see Figure 17: "Test circuit for inductive load switching and diode recovery times") - 3.3 A ISD = 1.0 A, di/dt = 100 A/µs, VDD = 25 V, Tj = 150 °C (see Figure 17: "Test circuit for inductive load switching and diode recovery times") - 229 ns - 377 nC - 3.3 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1)Pulse width limited by safe operating area (2)Pulsed: pulse duration = 300 µ s, duty cycle 1.5% DocID030308 Rev 1 5/15 Electrical characteristics 2.1 STD1NK60-1 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Capacitance variations 6/15 DocID030308 Rev 1 STD1NK60-1 Electrical characteristics Figure 8: Static drain-source on-resistance Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Source-drain forward characteristics Figure 12: Normalized V(BR)DSS vs temperature Figure 13: Maximum avalanche energy vs temperature DocID030308 Rev 1 7/15 Electrical characteristics STD1NK60-1 Figure 14: Maximum Id current vs Tc 8/15 DocID030308 Rev 1 STD1NK60-1 3 Test circuits Test circuits Figure 15: Test circuit for resistive load switching times Figure 16: Test circuit for gate charge behavior Figure 17: Test circuit for inductive load switching and diode recovery times Figure 18: Unclamped inductive load test circuit Figure 19: Unclamped inductive waveform Figure 20: Switching time waveform DocID030308 Rev 1 9/15 Package information 4 STD1NK60-1 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 IPAK (TO-251) type A package information Figure 21: IPAK (TO-251) type A package outline 10/15 DocID030308 Rev 1 STD1NK60-1 Package information Table 8: IPAK (TO-251) type A package mechanical data mm Dim. Min. Typ. Max. A 2.20 2.40 A1 0.90 1.10 b 0.64 0.90 b2 b4 0.95 5.20 B5 5.40 0.30 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 E 6.40 6.60 e e1 2.28 4.40 H 4.60 16.10 L 9.00 9.40 L1 0.80 1.20 L2 0.80 V1 10° DocID030308 Rev 1 1.00 11/15 Package information 4.2 STD1NK60-1 IPAK (TO-251) type C package information Figure 22: IPAK (TO-251) type C package outline 0068771_IK_typeC_rev14 12/15 DocID030308 Rev 1 STD1NK60-1 Package information Table 9: IPAK (TO-251) type C package mechanical data mm Dim. Min. Typ. Max. A 2.20 2.30 2.35 A1 0.90 1.00 1.10 b 0.66 0.79 0.90 b2 b4 5.23 c 0.46 0.59 c2 0.46 0.59 D 6.00 6.10 6.20 D1 5.20 5.37 5.55 E 6.50 6.60 6.70 E1 4.60 4.78 4.95 e 2.20 2.25 2.30 e1 4.40 4.50 4.60 H 16.18 16.48 16.78 L 9.00 9.30 9.60 L1 0.90 1.00 1.20 L2 0.90 1.08 1.25 θ1 3° 5° 7° θ2 1° 3° 5° DocID030308 Rev 1 5.33 5.43 13/15 Revision history 5 STD1NK60-1 Revision history Table 10: Document revision history 14/15 Date Revision 09-Feb-2017 1 DocID030308 Rev 1 Changes First release. STD1NK60-1 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved DocID030308 Rev 1 15/15