STD1NK60T4

STD1NK60T4 N-channel 600 V, 7.3 Ω typ., 1 A SuperMESH™ Power MOSFET in a DPAK package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STD1NK60T4 600 V 8.5 Ω 1A 30 W     Figure 1: Internal schematic diagram Applications    D(2, TAB) Extremely high dv/dt capability ESD improved capability 100% avalanche tested Gate charge minimized Low power battery chargers Swith mode low power supplies (SMPS) Low power, ballast, CFL (compact fluorescent lamps) Description G(1) S(3) AM01475v1_noZen This high voltage device is an N-channel Power MOSFET developed using the SuperMESH™ technology by STMicroelectronics, an optimization of the well-established PowerMESH™. In addition to a significant reduction in on-resistance, this device is designed to ensure a high level of dv/dt capability for the most demanding applications. Table 1: Device summary Order code Marking Package Packing STD1NK60T4 D1NK60 DPAK Tape and reel February 2017 DocID030307 Rev 1 This is information on a product in full production. 1/19 www.st.com Contents STD1NK60T4 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 9 4 Package information ..................................................................... 10 5 2/19 4.1 DPAK (TO-252) type A package information................................... 10 4.2 DPAK (TO-252) type C package information .................................. 13 4.3 Packing information ......................................................................... 16 Revision history ............................................................................ 18 DocID030307 Rev 1 STD1NK60T4 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 600 V VDGR Drain-gate voltage (RGS = 20 kΩ) 600 V VGS Gate-source voltage ±30 V ID Drain current (continuous) at TC = 25 °C 1.0 A ID Drain current (continuous) at TC = 100 °C 0.63 A IDM(1) Drain current (pulsed) 4 A PTOT Total dissipation at TC = 25 °C 30 W IAR Avalanche current, repetitive or not-repetitive (pulse width limited by Tjmax) 1 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 25 mJ Peak diode recovery voltage slope 3 V/ns - 55 to 150 °C Value Unit dv/dt (2) Tj Operating junction temperature range Tstg Storage temperature range Notes: (1)Pulse (2)I SD width limited by safe operating area. ≤ 1.0 A, di/dt ≤ 100 A/µs; VDD ≤ V(BR)DSS, TJ ≤ TJMAX Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 4.2 °C/W Rthj-amb Thermal resistance junction-ambient 100 °C/W DocID030307 Rev 1 3/19 Electrical characteristics 2 STD1NK60T4 Electrical characteristics TC = 25 ° C unless otherwise specified Table 4: On/off-state Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0 V, VDS = 600 V 1 µA VGS = 0 V, VDS = 600 V TC = 125 °C (1) 50 µA ±100 nA 3 3.7 V 7.3 8.5 Ω Typ. Max. Unit IDSS Zero gate voltage drain current IGSS Gate body leakage current VDS=0 V, VGS= ±30 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 0.5 A 2.25 Notes: (1)Defined by design, not subject to production test. Table 5: Dynamic Symbol Parameter Test conditions Min. Ciss Input capacitance - 156 - pF Coss Output capacitance - 23.5 - pF Crss Reverse transfer capacitance - 3.8 - pF Qg Total gate charge - 7 - nC Qgs Gate-source charge - 1.1 - nC Qgd Gate-drain charge - 3.7 - nC Min. Typ. Max. Unit - 6.5 - ns - 5 - ns - 19 - ns - 25 - ns VDS = 25 V, f = 1 MHz, VGS = 0 V VDD = 480 V, ID = 1 A VGS= 0 to 10 V (see Figure 16: "Test circuit for gate charge behavior") Table 6: Switching times Symbol td(on) tr td(off) tf 4/19 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD= 300 V, ID = 0.5 A, RG = 4.7 Ω VGS = 10 V (see Figure 15: "Test circuit for resistive load switching times" and Figure 20: "Switching time waveform") DocID030307 Rev 1 STD1NK60T4 Electrical characteristics Table 7: Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 1 A ISDM(1) Source-drain current (pulsed) - 4 A VSD(2) Forward on voltage ISD = 1.0 A, VGS = 0 V - 1.6 V trr Reverse recovery time - 140 ns Qrr Reverse recovery charge - 240 nC IRRM Reverse recovery current ISD = 1.0 A, di/dt = 100 A/µs, VDD = 25 V, (see Figure 17: "Test circuit for inductive load switching and diode recovery times") - 3.3 A ISD = 1.0 A, di/dt = 100 A/µs, VDD = 25 V, Tj = 150 °C (see Figure 17: "Test circuit for inductive load switching and diode recovery times") - 229 ns - 377 nC - 3.3 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1)Pulse width limited by safe operating area (2)Pulsed: pulse duration = 300 µ s, duty cycle 1.5% DocID030307 Rev 1 5/19 Electrical characteristics 2.1 STD1NK60T4 Electrical characteristics (curves) Figure 3: Thermal impedance Figure 2: Safe operating area CG34360 K 0 10 c -1 10 -2 10 -5 10 6/19 -4 10 -3 10 -2 10 -1 10 tp (s) Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Capacitance variations DocID030307 Rev 1 STD1NK60T4 Electrical characteristics Figure 8: Static drain-source on-resistance Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Source-drain forward characteristics Figure 12: Normalized V(BR)DSS vs temperature Figure 13: Maximum avalanche energy vs temperature DocID030307 Rev 1 7/19 Electrical characteristics STD1NK60T4 Figure 14: Maximum Id current vs Tc 8/19 DocID030307 Rev 1 STD1NK60T4 3 Test circuits Test circuits Figure 15: Test circuit for resistive load switching times Figure 16: Test circuit for gate charge behavior Figure 17: Test circuit for inductive load switching and diode recovery times Figure 18: Unclamped inductive load test circuit Figure 19: Unclamped inductive waveform Figure 20: Switching time waveform DocID030307 Rev 1 9/19 Package information 4 STD1NK60T4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 DPAK (TO-252) type A package information Figure 21: DPAK (TO-252) type A package outline 0068772_A_21 10/19 DocID030307 Rev 1 STD1NK60T4 Package information Table 8: DPAK (TO-252) type A mechanical data mm Dim. Min. Typ. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 4.60 4.70 4.80 e 2.16 2.28 2.40 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 (L1) 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 5.10 5.25 6.60 1.00 0.20 0° DocID030307 Rev 1 8° 11/19 Package information STD1NK60T4 Figure 22: DPAK (TO-252) recommended footprint (dimensions are in mm) 12/19 DocID030307 Rev 1 STD1NK60T4 4.2 Package information DPAK (TO-252) type C package information Figure 23: DPAK (TO-252) type C package outline 0068772_C_21 DocID030307 Rev 1 13/19 Package information STD1NK60T4 Table 9: DPAK (TO-252) type C mechanical data mm Dim. Min. Typ. Max. A 2.20 2.30 2.38 A1 0.90 1.01 1.10 A2 0.00 0.10 b 0.72 0.85 b4 5.13 5.46 c 0.47 0.60 c2 0.47 0.60 D 6.00 D1 5.25 E 6.50 E1 4.70 e 6.10 6.20 6.60 6.70 2.186 2.286 2.386 H 9.80 10.10 10.40 L 1.40 1.50 1.70 L1 L2 2.90 REF 0.90 L3 L4 1.25 0.51 BSC 0.60 L6 14/19 5.33 0.80 1.00 1.80 BSC θ1 5° 7° 9° θ2 5° 7° 9° V2 0° DocID030307 Rev 1 8° STD1NK60T4 Package information Figure 24: DPAK (TO-252) recommended footprint (dimensions are in mm) FP_0068772_21 DocID030307 Rev 1 15/19 Package information 4.3 STD1NK60T4 Packing information Figure 25: DPAK (TO-252) tape outline 16/19 DocID030307 Rev 1 STD1NK60T4 Package information Figure 26: DPAK (TO-252) reel outline Table 10: DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 B1 D 1.5 D1 1.5 E 1.65 F 1.6 Min. Max. 330 13.2 D 20.2 G 16.4 1.85 N 50 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 DocID030307 Rev 1 18.4 22.4 17/19 Revision history 5 STD1NK60T4 Revision history Table 11: Document revision history 18/19 Date Revision 06-Feb-2017 1 DocID030307 Rev 1 Changes First release. STD1NK60T4 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved DocID030307 Rev 1 19/19