STD20NF06LT4

STD20NF06L Datasheet N-channel 60 V, 32 mΩ typ., 24 A, STripFET II Power MOSFET in a DPAK package Features TAB 2 3 1 • • • DPAK Order code VDS RDS(on) max. ID PTOT STD20NF06L 60 V 40 mΩ 24 A 60 W Exceptional dv/dt capability 100% avalanche tested Low gate charge D(2, TAB) Applications • G(1) Switching applications Description S(3) AM01475v1_noZen This Power MOSFET has been developed using STMicroelectronics' unique STripFET process, which is specifically designed to minimize input capacitance and gate charge. This renders the device suitable for use as primary switch in advanced high-efficiency isolated DC-DC converters for telecom and computer applications, and applications with low gate charge driving requirements. Product status link STD20NF06L Product summary Order code STD20NF06LT4 Marking D20NF06L Package DPAK Packing Tape and reel DS3367 - Rev 5 - April 2022 For further information contact your local STMicroelectronics sales office. www.st.com STD20NF06L Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 60 V VGS Gate-source voltage ±18 V Drain current (continuous) at TC = 25 °C 24 Drain current (continuous) at TC = 100 °C 17 IDM(1) Drain current (pulsed) 96 A PTOT Total power dissipation at TC = 25 °C 60 W ID A Derating factor 0.4 W/°C dv/dt(2) Peak diode recovery voltage slope 10 V/ns EAS(3) Single pulse avalanche energy 225 mJ -55 to 175 °C Value Unit Tstg TJ Storage temperature range Operating junction temperature range 1. Pulse width is limited by safe operating area. 2. ISD ≤ 24 A, di/dt ≤ 300 A/ns, VDD = 80% V(BR)DSS 3. Starting TJ = 25 °C, ID = IAR A, VDD = 45 V. Table 2. Thermal data Symbol Parameter RthJC Thermal resistance, junction-to-case 2.5 RthJB(1) Thermal resistance, junction-to-board 50 °C/W 1. When mounted on a 1-inch² FR-4, 2 Oz copper board. DS3367 - Rev 5 page 2/15 STD20NF06L Electrical characteristics 2 Electrical characteristics (TC = 25 °C unless otherwise specified). Table 3. Static Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions VGS = 0 V, ID = 250 µA Min. Typ. Max. 60 Unit V VGS = 0 V, VDS = 60 V 1 IDSS Zero gate voltage drain current VGS = 0 V, VDS = 60 V, TC = 125 °C(1) 10 IGSS Gate-body leakage current VDS = 0 V, VGS = ±18 V ±100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2.5 V RDS(on) Static drain-source on-resistance 1 VGS = 10 V, ID = 12 A 32 VGS = 5 V, ID = 12 A 40 50 µA mΩ 1. Defined by design, not subject to production test. Table 4. Dynamic Symbol gfs Forward transconductance Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance td(on) Turn-on delay time tr td(off) tf DS3367 - Rev 5 Parameter Rise time Turn-off delay time Test conditions VDS = 25 V, ID = 12 A VDS = 25 V, f = 1 MHz, VGS = 0 V VDD = 30 V, ID = 10 A, RG = 4.7 Ω, VGS = 10 V (see Figure 11. Test circuit for resistive load switching times) Fall time Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VDD = 30 V, ID = 20 A, VGS = 10 V, RG = 4.7 Ω (see Figure 12. Test circuit for gate charge behavior) Min. Typ. Max. Unit - 20 - S - 660 - pF - 170 - pF - 70 - pF - 11 - ns - 50 - ns - 20 - ns - 12 - ns - 13 - nC - 3.5 - nC - 8 - nC page 3/15 STD20NF06L Electrical characteristics Table 5. Source-drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 24 A ISDM Source-drain current (pulsed) - 96 A VSD(2) Forward on voltage VGS = 0 V, ISD = 20 A - 1.5 V trr Reverse recovery time ISD = 20 A, di/dt = 100 A/µs, - 56 ns Qrr Reverse recovery charge VDD = 20 V, TJ = 150 °C - 108 nC IRRM Reverse recovery current (see Figure 13. Test circuit for inductive load switching and diode recovery times) - 4 A (1) 1. Pulse width is limited by safe operating area. 2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DS3367 - Rev 5 page 4/15 STD20NF06L Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characteristics Figure 4. Transfer characteristics Figure 5. Static drain-source on-resistance Figure 6. Gate charge vs gate-source voltage DS3367 - Rev 5 page 5/15 STD20NF06L Electrical characteristics (curves) Figure 7. Capacitance variations Figure 8. Normalized gate threshold voltage vs temperature Figure 9. Normalized on-resistance vs temperature Figure 10. Normalized V(BR)DSS vs temperature DS3367 - Rev 5 page 6/15 STD20NF06L Test circuits 3 Test circuits Figure 11. Test circuit for resistive load switching times Figure 12. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 13. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A A L 100 µH fast diode B B B G RG VD 3.3 µF D + Figure 14. Unclamped inductive load test circuit 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S _ D.U.T. Vi pulse width AM01470v1 AM01471v1 Figure 15. Unclamped inductive waveform Figure 16. Switching time waveform ton V(BR)DSS td(on) toff td(off) tr tf VD 90% 90% IDM VDD VDD VGS 0 AM01472v1 DS3367 - Rev 5 10% 0 ID VDS 10% 90% 10% AM01473v1 page 7/15 STD20NF06L Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 DPAK (TO-252) package information Figure 17. DPAK (TO-252) type A package outline 0068772_A_30 DS3367 - Rev 5 page 8/15 STD20NF06L DPAK (TO-252) package information Table 6. DPAK (TO-252) type A mechanical data Dim. mm Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 4.60 4.70 4.80 e 2.159 2.286 2.413 e1 4.445 4.572 4.699 H 9.35 10.10 L 1.00 1.50 (L1) 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 DS3367 - Rev 5 Typ. 5.10 5.25 6.60 1.00 0.20 0° 8° page 9/15 STD20NF06L DPAK (TO-252) package information Figure 18. DPAK (TO-252) recommended footprint (dimensions are in mm) FP_0068772_31 DS3367 - Rev 5 page 10/15 STD20NF06L DPAK (TO-252) packing information 4.2 DPAK (TO-252) packing information Figure 19. DPAK (TO-252) tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 K0 For machine ref. only including draft and radii concentric around B0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 DS3367 - Rev 5 page 11/15 STD20NF06L DPAK (TO-252) packing information Figure 20. DPAK (TO-252) reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 7. DPAK (TO-252) tape and reel mechanical data Tape Dim. mm mm Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 DS3367 - Rev 5 Reel Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 18.4 22.4 page 12/15 STD20NF06L Revision history Table 8. Document revision history DS3367 - Rev 5 Date Revision Changes 19-Apr-2005 2 Added package IPAK 08-Jun-2006 3 Graphical updates 03-Jul-2006 4 New template, no content change 29-Apr-2022 5 The part number STD20NF06L-1 has been removed and the document has been updated accordingly. page 13/15 STD20NF06L Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 DPAK (TO-252) package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DS3367 - Rev 5 page 14/15 STD20NF06L IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS3367 - Rev 5 page 15/15