STD25NF10LT4

STD25NF10L N-CHANNEL 100V - 0.030 Ω - 25A DPAK LOW GATE CHARGE STripFET™ II POWER MOSFET TYPE STD25NF10L ■ ■ ■ ■ ■ ■ VDSS RDS(on) ID 100 V < 0.035 Ω 25 A TYPICAL RDS(on) = 0.030 Ω EXCEPTIONAL dv/dt CAPABILITY 100% AVALANCHE TESTED LOW THRESHOLD DEVICE LOGIC LEVEL DEVICE SURFACE-MOUNTING DPAK (TO-252) POWER PACKAGE IN TAPE & REEL (SUFFIX “T4") 3 1 DPAK TO-252 (Suffix “T4”) DESCRIPTION This MOSFET series realized with STMicroelectronics unique STripFET process has specifically been designed to minimize input capacitance and gate charge. It is therefore suitable as primary switch in advanced highefficiency, high-frequency isolated DC-DC converters for Telecom and Computer applications. It is also intended for any applications with low gate drive requirements INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ HIGH-EFFICIENCY DC-DC CONVERTERS ■ UPS AND MOTOR CONTROL ABSOLUTE MAXIMUM RATINGS Symbol VDS Parameter Drain-source Voltage (VGS = 0) Value Unit 100 V Drain-gate Voltage (RGS = 20 kΩ) 100 V VGS Gate- source Voltage ± 16 V ID(*) Drain Current (continuous) at TC = 25°C 25 A ID Drain Current (continuous) at TC = 100°C 25 A VDGR IDM(•) Ptot dv/dt (1) EAS (2) Tstg Tj Drain Current (pulsed) 100 A Total Dissipation at TC = 25°C 100 W Derating Factor 0.67 W/°C Peak Diode Recovery voltage slope 20 V/ns Single Pulse Avalanche Energy 450 mJ -55 to 175 °C Storage Temperature Max. Operating Junction Temperature (•) Pulse width limited by safe operating area. (*) Current Limited by Package February 2003 (1) ISD ≤25A, di/dt ≤300A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX (2) Starting T j = 25 oC, ID = 12.5A, VDD = 50V 1/9 STD25NF10L THERMAL DATA Rthj-case Rthj-pcb Tl Thermal Resistance Junction-case Thermal Resistance Junction-pcb(#) Maximum Lead Temperature For Soldering Purpose Max Max 1.5 50 275 °C/W °C/W °C (#) When Mounted on 1 inch2 FR-4 board, 2 oz of Cu. ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol Parameter Test Conditions Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating TC = 125°C IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 16 V V(BR)DSS Min. Typ. Max. 100 Unit V 1 10 µA µA ±100 nA Max. Unit 2.5 V 0.030 0.035 0.035 0.040 Ω Ω Typ. Max. Unit ON (*) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS ID = 250 µA RDS(on) Static Drain-source On Resistance VGS = 10 V VGS = 4.5 V ID = 12.5 A ID = 12.5 A Min. Typ. 1 DYNAMIC Symbol 2/9 Parameter Test Conditions gfs (*) Forward Transconductance VDS = 15 V Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25V f = 1 MHz VGS = 0 ID = 12.5 A Min. 24 S 1710 250 110 pF pF pF STD25NF10L ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time ID = 12.5 A VDD = 50 V RG = 4.7 Ω VGS = 5 V (Resistive Load, Figure 3) 20 40 Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD= 80 V ID= 25 A VGS= 5 V 38 8.5 21 52 nC nC nC Typ. Max. Unit ns ns SWITCHING OFF Symbol td(off) tf Parameter Test Conditions Min. ID = 12.5 A VDD = 50 V RG = 4.7Ω, VGS = 5 V (Resistive Load, Figure 3) Turn-off Delay Time Fall Time 58 20 ns ns SOURCE DRAIN DIODE Symbol Parameter ISD ISDM (•) Source-drain Current Source-drain Current (pulsed) VSD (*) Forward On Voltage ISD = 25 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current di/dt = 100A/µs ISD = 25 A VDD = 50 V Tj = 150°C (see test circuit, Figure 5) trr Qrr IRRM (*)Pulsed: Pulse duration = 300 µs, duty cycle (•)Pulse width limited by safe operating area. Safe Operating Area Test Conditions Min. Typ. VGS = 0 88 317 7.2 Max. Unit 25 100 A A 1.5 V ns nC A 1.5 %. Thermal Impedance 3/9 STD25NF10L Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/9 STD25NF10L Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized Breakdown Voltage vs Temperature . . 5/9 STD25NF10L Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/9 STD25NF10L TO-252 (DPAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A2 0.03 0.23 0.001 0.009 B 0.64 0.9 0.025 0.035 B2 5.2 5.4 0.204 0.212 C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 E 6.4 6.6 0.252 0.260 G 4.4 4.6 0.173 0.181 H 9.35 10.1 0.368 0.397 L2 0.8 L4 0.031 0.6 1 0.023 0.039 A1 C2 A H A2 C DETAIL "A" L2 D = 1 = G 2 = = = E = B2 3 B DETAIL "A" L4 0068772-B 7/9 STD25NF10L 8/9 STD25NF10L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics  2002 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 9/9