STD30N10F7

STD30N10F7 N-channel 100 V, 0.02 Ω typ., 32 A, STripFET™ F7 Power MOSFET in a DPAK package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STD30N10F7 100 V 0.024 Ω 32 A 50 W     Figure 1: Internal schematic diagram Among the lowest RDS(on) on the market Excellent FoM (figure of merit) Low Crss/Ciss ratio for EMI immunity High avalanche ruggedness Applications  Switching applications D(2, TAB) Description This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low onstate resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. G(1) S(3) AM01475v1_noZen Table 1: Device summary Order code Marking Package Packing STD30N10F7 30N10F7 DPAK Tape and reel May 2017 DocID025607 Rev 4 This is information on a product in full production. 1/15 www.st.com Contents STD30N10F7 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/15 4.1 DPAK (TO-252) type A package information..................................... 9 4.2 DPAK (TO-252) packing information ............................................... 12 Revision history ............................................................................ 14 DocID025607 Rev 4 STD30N10F7 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 100 V VGS Gate-source voltage ±20 V Drain current (continuous) at TC = 25 °C 32 Drain current (continuous) at TC = 100 °C 23 IDM(1) Drain current (pulsed) at TC = 25 °C 132 A PTOT Total dissipation at TC = 25 °C 50 W ID TJ Operating junction temperature range Tstg Storage temperature range -55 to 175 A °C °C Notes: (1)Pulse width is limited by safe operating area Table 3: Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter Value Thermal resistance junction-case 3 Thermal resistance junction-pcb 50 Unit °C/W Notes: (1)When mounted on a 1-inch² FR-4, 2 Oz copper board. DocID025607 Rev 4 3/15 Electrical characteristics 2 STD30N10F7 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 4: Static Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 250 μA Min. Typ. Max. 100 Unit V VGS = 0 V, VDS = 100 V 1 VGS = 0 V, VDS = 100 V, TC = 125 °C(1) 100 Gate-body leakage current VDS = 0 V, VGS = ±20 V 100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 4.5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 16 A 0.02 0.024 Ω Min. Typ. Max. Unit - 1270 - pF - 290 - pF - 24 - pF - 19 - nC - 9 - nC - 4.5 - nC Test conditions Min. Typ. Max. Unit VDD = 50 V, ID = 16 A, RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform") - 12 - ns - 17.5 - ns - 22 - ns - 5.6 - ns IDSS Zero gate voltage drain current IGSS 2.5 µA Notes: (1)Defined by design, not subject to production test. Table 5: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS = 50 V, f = 1 MHz, VGS = 0 V VDD = 50 V, ID = 32 A, VGS = 0 to 10 V (see Figure 14: "Test circuit for gate charge behavior") Table 6: Switching times Symbol td(on) tr td(off) tf 4/15 Parameter Turn-on delay time Rise time Turn-off delay time Fall time DocID025607 Rev 4 STD30N10F7 Electrical characteristics Table 7: Source-drain diode Symbol VSD(1) Parameter Test conditions Min. Typ. Max. Unit 1.1 V Forward on voltage VGS = 0 V, ISD = 32 A - trr Reverse recovery time - 41 ns Qrr Reverse recovery charge - 47 nC IRRM Reverse recovery current ISD = 32 A, di/dt = 100 A/µs, VDD = 80 V, TJ = 150 °C (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 2.3 A Notes: (1)Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID025607 Rev 4 5/15 Electrical characteristics 2.1 STD30N10F7 Electrical characteristics (curves) Figure 3: Thermal impedance Figure 2: Safe operating area ID (A) 100 d 0.2 0.1 0.05 0.02 Operation in this area is limited by RDS(on) 10 0.01 100µs 1 1ms 10ms 0.1 Tj=175°C Tc=25°C Single pulse 0.01 0.1 1 10 VDS(V) Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/15 DocID025607 Rev 4 STD30N10F7 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Source-drain diode forward characteristics Figure 12: Normalized V(BR)DSS vs temperature µ DocID025607 Rev 4 7/15 Test circuits 3 8/15 STD30N10F7 Test circuits Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform DocID025607 Rev 4 STD30N10F7 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 DPAK (TO-252) type A package information Figure 19: DPAK (TO-252) type A package outline DocID025607 Rev 4 9/15 Package information STD30N10F7 Table 8: DPAK (TO-252) type A mechanical data mm Dim. Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 4.60 4.70 4.80 e 2.16 2.28 2.40 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 (L1) 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 10/15 Typ. 5.10 5.25 6.60 1.00 0.20 0° DocID025607 Rev 4 8° STD30N10F7 Package information Figure 20: DPAK (TO-252) type A recommended footprint (dimensions are in mm) DocID025607 Rev 4 11/15 Package information 4.2 STD30N10F7 DPAK (TO-252) packing information Figure 21: DPAK (TO-252) tape outline 12/15 DocID025607 Rev 4 STD30N10F7 Package information Figure 22: DPAK (TO-252) reel outline Table 9: DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 B1 D 1.5 D1 1.5 E 1.65 F 1.6 Min. Max. 330 13.2 D 20.2 G 16.4 1.85 N 50 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 DocID025607 Rev 4 18.4 22.4 13/15 Revision history 5 STD30N10F7 Revision history Table 10: Document revision history Date Revision 28-Nov-2013 1 First release 2 – Updated: Figure 13,14,15 and Figure 16 – Updated: Section 4.1: DPAK,STD30N10F7 – Minor text changes. 3 – Updated title – Updated Section 2: Electrical characteristics – Updated Section 4: Package information – Minor text changes. 4 Modified Table 2: "Absolute maximum ratings". Updated Section 4: "Package information". Minor text changes. 03-Apr-2014 27-Jan-2016 16-May-2017 14/15 Changes DocID025607 Rev 4 STD30N10F7 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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