®
STD30NF03L
N - CHANNEL 30V - 0.020 Ω - 30A DPAK STripFET™ POWER MOSFET
TYPE STD30NF03L
s s s
V DSS 30 V
R DS(o n) < 0.025 Ω
ID 30 A
TYPICAL RDS(on) = 0.020 Ω LOW THRESHOLD DRIVE ADD SUFFIX ”T4” FOR ORDERING IN TAPE & REEL
3 1
DESCRIPTION This Power MOSFET is the latest development of STMicroelectronics unique ”Single Feature Size™” strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s SOLENOID AND RELAY DRIVERS s MOTOR CONTROL, AUDIO AMPLIFIERS s DC-DC & DC-AC CONVERTERS
DPAK TO-252
(Suffix ”T4”)
I NTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symb ol V DS V DGR VGS I D( • ) ID I DM ( •• ) P tot E AS ( 1 ) T st g Tj Parameter Drain-source Voltage (VGS = 0) Drain- gate Voltage (R GS = 20 k Ω ) G ate-source Voltage Drain Current (continuous) at Tc = 25 oC Drain Current (continuous) at Tc = 100 o C Drain Current (pulsed) T otal Dissipation at Tc = 25 C Derating Factor Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature
o
Value 30 30 ± 20 30 19 120 40 0.27 100 -65 to 175 175
( 1) starting Tj = 25 oC, ID = 15A , VDD = 15V
Unit V V V A A A W W /o C m/J
o o
C C
(••) Pulse width limited by safe operating area (•)Current limited by the package
October 1999
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STD30NF03L
THERMAL DATA
R th j-pc b R thj -amb R t hj-s ink Tl Thermal Resistance Junction-PC Board Max Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink T yp Maximum Lead Temperature F or Soldering Purpose 3.75 100 1.5 275
o o
C/W C/W o C/W o C
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF
Symbo l V (BR)DSS I DSS IGSS Parameter Drain-source Breakdown Voltage Test Con ditions I D = 250 µ A V GS = 0 Min. 30 1 10 ± 100 Typ. Max. Unit V µA µA nA
V DS = Max Rating Zero Gate Voltage Drain Current (V GS = 0) V DS = Max Rating Gate-body Leakage Current (VDS = 0) V GS = ± 20 V
T c = 125 oC
ON (∗)
Symbo l V GS(th) R DS(on) I D(o n) Parameter Gate Threshold Voltage V DS = V GS Static Drain-source On Resistance On State Drain Current V GS = 10 V V GS = 4.5 V Test Con ditions ID = 250 µ A I D = 15 A I D = 15 A 30 Min. 1 Typ. 1.7 0.020 0.028 Max. 2.5 0.025 0.035 Unit V Ω Ω A
V DS > ID(o n) x R DS(on )ma x V GS = 10 V
DYNAMIC
Symbo l g f s (∗ ) C iss C os s C rss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Con ditions V DS > ID(o n) x R DS(on )ma x V DS = 25 V f = 1 MHz I D = 15 A V GS = 0 V Min. Typ. 13 830 230 92 Max. Unit S pF pF pF
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STD30NF03L
ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON
Symbo l t d(on) tr Qg Q gs Q gd Parameter Turn-on Delay T ime Rise Time Total G ate Charge Gate-Source Charge Gate-Drain Charge Test Con ditions V DD = 15 V I D = 20 A R G = 4.7 Ω V GS = 4.5 V (Resistive Load, see fig. 3) V DD = 24 V ID = 30 A V GS = 5 V Min. Typ. 35 205 18 7 8 Max. Unit ns ns nC nC nC
SWITCHING OFF
Symbo l t d(of f) tf Parameter Turn-off Delay T ime Fall T ime Test Con ditions V DD = 15 V I D = 20 A V GS = 4.5 V R G = 4.7 Ω (Resistive Load, see fig. 3) Min. Typ. 90 240 Max. Unit ns ns
SOURCE DRAIN DIODE
Symbo l ISD I SDM (• ) V SD ( ∗ ) t rr Q rr I RRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 30 A V GS = 0 65 72 2 I SD = 40 A di/dt = 100 A/ µ s T j = 150 o C V DD = 15 V (see test circuit, fig. 5) Test Con ditions Min. Typ. Max. 30 120 1.5 Unit A A V ns nC A
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area
Safe Operating Area
Thermal Impedance
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STD30NF03L
Output Characteristics Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
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STD30NF03L
Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
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STD30NF03L
Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
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STD30NF03L
TO-252 (DPAK) MECHANICAL DATA
mm MIN. A A1 A2 B B2 C C2 D E G H L2 L4 0.6 2.2 0.9 0.03 0.64 5.2 0.45 0.48 6 6.4 4.4 9.35 0.8 1 0.023 TYP. MAX. 2.4 1.1 0.23 0.9 5.4 0.6 0.6 6.2 6.6 4.6 10.1 MIN. 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 0.252 0.173 0.368 0.031 0.039 inch TYP. MAX. 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 0.260 0.181 0.397
DIM.
H
A
C2
C
DETAIL ”A”
A1
L2
D DETAIL ”A” B
=
=
3
B2
=
=
G
E
2
L4
1
=
=
A2
0068772-B
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STD30NF03L
Information furnished is believed to be accurate and reliable. However, STMicroelect onics assumes no responsibil ity for the consequences r of use of such information nor for any infringement of patents or other rights of third partes which may result from its use. No license is i granted by implication or otherwise under any patent or patent rights of STMicroelectro nics. Specific ation mentioned in this publication are subjec t to change without notice. This publication supersedes and replaces all informaton previously supplied. STMicroelectronics products i are not authorized for use as critical components in life support devices or systems with express written approval of STMicroelectronics. out The ST logo is a trademark of STMicroelectronics © 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japa - Malaysia - Malta - Morocco n Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
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