STD35NF3LL-1

N-CHANNEL 30V - 0.014 Ω - 35A IPAK/DPAK STripFET™ II POWER MOSFET TYPE STD35NF3LL STD35NF3LL-1 s s s s s s STD35NF3LL STD35NF3LL-1 VDSS 30 V 30 V RDS(on) < 0.0195 Ω < 0.0195 Ω ID 35 A 35 A s TYPICAL RDS(on) = 0.016 Ω @ 4.5V OPTIMAL RDS(on) x Qg TRADE-OFF @ 4.5V CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED LOW THRESHOLD DRIVE THROUGH-HOLE IPAK (TO-251) POWER PACKAGE IN TUBE (SUFFIX “-1") SURFACE-MOUNTING DPAK (TO-252) POWER PACKAGE IN TAPE & REEL (SUFFIX “T4") 3 2 1 IPAK TO-251 (Suffix “-1”) DPAK TO-252 (Suffix “T4”) 3 1 DESCRIPTION This application specific Power MOSFET is the third genaration of STMicroelectronis unique "Single Feature Size™" strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high efficiency are of paramount importance. INTERNAL SCHEMATIC DIAGRAM APPLICATIONS s SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY DC/DC CONVERTERS ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID ID IDM(•) Ptot EAS (1) Tstg Tj February 2002 . Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuos) at TC = 25°C Drain Current (continuos) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature Value 30 30 ± 16 35 25 140 50 0.33 300 -55 to 175 (1) Starting T j = 25 oC, ID = 17.5 A, VDD= 24 V Unit V V V A A A W W/°C mJ °C (•) Pulse width limited by safe operating area. 1/10 STD35NF3LL/STD35NF3LL-1 THERMAL DATA Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature For Soldering Purpose Max Max Typ 3 100 300 °C/W °C/W °C ELECTRICAL CHARACTERISTICS (Tcase = 25 °C unless otherwise specified) OFF Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 µA, VGS = 0 VDS = Max Rating VDS = Max Rating TC = 100°C VGS = ± 16 V Min. 30 1 10 ±100 Typ. Max. Unit V µA µA nA ON (*) Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS VGS = 10 V VGS = 4.5 V ID = 250 µA ID = 17.5 A ID = 17.5 A Min. 1 0.014 0.016 0.0195 0.0215 Typ. Max. Unit V Ω Ω DYNAMIC Symbol gfs (*) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS =15 V ID = 17.5 A Min. Typ. 19 800 250 60 Max. Unit S pF pF pF VDS = 25V, f = 1 MHz, VGS = 0 2/10 STD35NF3LL/STD35NF3LL-1 ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions ID = 17.5 A VDD = 15 V RG = 4.7 Ω VGS = 4.5 V (Resistive Load, Figure 3) VDD = 24 V ID = 35 A VGS= 5V Min. Typ. 17 100 12.5 4.2 5.2 17 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions ID = 17.5 A VDD = 15 V RG = 4.7 Ω VGS = 4.5 V (Resistive Load, Figure 3) Min. Typ. 20 21 Max. Unit ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (•) VSD (*) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 35 A VGS = 0 35 44 2.5 Test Conditions Min. Typ. Max. 35 140 1.3 Unit A A V ns nC A di/dt = 100A/µs ISD = 35 A VDD = 15 V Tj = 150°C (see test circuit, Figure 5) (*)Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (•)Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/10 STD35NF3LL/STD35NF3LL-1 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/10 STD35NF3LL/STD35NF3LL-1 Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized Breakdown Voltage vs Temperature. . . 5/10 STD35NF3LL/STD35NF3LL-1 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/10 STD35NF3LL/STD35NF3LL-1 TO-251 (IPAK) MECHANICAL DATA DIM. MIN. A A1 A3 B B2 B3 B5 B6 C C2 D E G H L L1 L2 0.45 0.48 6 6.4 4.4 15.9 9 0.8 0.8 0.3 0.95 0.6 0.6 6.2 6.6 4.6 16.3 9.4 1.2 1 0.017 0.019 0.236 0.252 0.173 0.626 0.354 0.031 0.031 2.2 0.9 0.7 0.64 5.2 mm TYP. MAX. 2.4 1.1 1.3 0.9 5.4 0.85 0.012 0.037 0.023 0.023 0.244 0.260 0.181 0.641 0.370 0.047 0.039 MIN. 0.086 0.035 0.027 0.025 0.204 inch TYP. MAX. 0.094 0.043 0.051 0.031 0.212 0.033 H C A C2 L2 D B3 B6 A1 L = = 3 B5 B A3 = B2 = G = E L1 1 2 = 0068771-E 7/10 STD35NF3LL/STD35NF3LL-1 TO-252 (DPAK) MECHANICAL DATA mm MIN. A A1 A2 B B2 C C2 D E G H L2 L4 0.6 2.2 0.9 0.03 0.64 5.2 0.45 0.48 6 6.4 4.4 9.35 0.8 1 0.023 TYP. MAX. 2.4 1.1 0.23 0.9 5.4 0.6 0.6 6.2 6.6 4.6 10.1 MIN. 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 0.252 0.173 0.368 0.031 0.039 inch TYP. MAX. 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 0.260 0.181 0.397 DIM. H A C2 C DETAIL "A" A1 L2 D DETAIL "A" B = = 3 B2 = = G E 2 L4 1 = = A2 0068772-B 8/10 STD35NF3LL/STD35NF3LL-1 DPAK FOOTPRINT TUBE SHIPMENT (no suffix)* All dimensions are in millimeters All dimensions are in millimeters TAPE AND REEL SHIPMENT (suffix ”T4”)* REEL MECHANICAL DATA DIM. A B C D G N T 1.5 12.8 20.2 16.4 50 22.4 18.4 13.2 mm MIN. MAX. 330 0.059 0.504 0.520 0.795 0.645 0.724 1.968 0.881 BULK QTY 1000 inch MIN. MAX. 12.992 TAPE MECHANICAL DATA DIM. A0 B0 B1 D D1 E F K0 P0 P1 P2 R W 1.5 1.5 1.65 7.4 2.55 3.9 7.9 1.9 40 15.7 1.85 7.6 2.75 4.1 8.1 2.1 16.3 BASE QTY 1000 mm MIN. 6.8 10.4 MAX. 7 10.6 12.1 1.6 inch MIN. MAX. 0.267 0.275 0.409 0.417 0.476 0.059 0.063 0.059 0.065 0.073 0.291 0.299 0.100 0.108 0.153 0.161 0.311 1.574 0.618 0.319 0.075 0.082 0.641 *on sales type 9/10 STD35NF3LL/STD35NF3LL-1 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics ® 2002 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 10/10