STD3LN80K5

STD3LN80K5 N-channel 800 V, 2.75 Ω typ., 2 A MDmesh™ K5 Power MOSFET in a DPAK package Datasheet - production data Features Order code STD3LN80K5      V DS 800 V RDS(on) max ID 3.25 Ω 2A Industry’s lowest RDS(on) x area Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Figure 1: Internal schematic diagram Applications D(2, TAB)  Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. G(1) S(3) AM01476v1 Table 1: Device summary Order code Marking Package Packing STD3LN80K5 3LN80K5 DPAK Tape and reel July 2016 DocID027714 Rev 2 This is information on a product in full production. 1/15 www.st.com Contents STD3LN80K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/15 4.1 DPAK package information ............................................................... 9 4.2 DPAK packing information .............................................................. 12 Revision history ............................................................................ 14 DocID027714 Rev 2 STD3LN80K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter VGS Gate-source voltage Value Unit ± 30 V ID Drain current (continuous) at TC = 25 °C 2 A ID Drain current (continuous) at TC = 100 °C 1.25 A Drain current (pulsed) 8 A W ID(1) PTOT Total dissipation at TC = 25 °C 45 dv/dt (2) Peak diode recovery voltage slope 4.5 dv/dt (3) MOSFET dv/dt ruggedness 50 Tstg Storage temperature range Tj Operating junction temperature range V/ns - 55 to 150 °C Notes: (1)Pulse (2)I SD (3)V width limited by safe operating area. ≤ 2 A, di/dt ≤ 100 A/µs; VDSpeak < V(BR)DSS, VDD = 640 V DS ≤ 640 V. Table 3: Thermal data Symbol Parameter Rthj-case Rthj-pcb (1) Value Unit Thermal resistance junction-case 2.78 °C/W Thermal resistance junction-pcb 50 °C/W Notes: (1)When mounted on 1inch² FR-4 board, 2 oz Cu. Table 4: Avalanche characteristics Symbol Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by T jmax) 0.7 A EAS Single pulse avalanche energy (starting Tj = 25°C, ID = IAR; VDD = 50 V) 155 mJ DocID027714 Rev 2 Value Unit 3/15 Electrical characteristics 2 STD3LN80K5 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 5: On /off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage ID = 1 mA, VGS = 0 V Min. Typ. Max. 800 Unit V VDS = 800 V, VGS = 0 V 1 µA VDS = 800 V, VGS = 0 V, TC = 125 °C(1) 50 µA Gate body leakage current VGS = ± 20 V, VGS = 0 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 4 5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 1 A 2.75 3.25 Ω Min. Typ. Max. Unit - 102 - pF - 11 - pF - 0.1 - pF - 20 - pF - 7 - pF IDSS Zero gate voltage drain current IGSS 3 Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Ciss Parameter Test conditions Input capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance Cotr(1) Equivalent capacitance time related VDS = 0 to 640 V, VGS = 0 V Coer(2) Equivalent capacitance energy related RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 12 - Ω Qg Total gate charge - 2.63 - nC Qgs Gate-source charge - 0.91 - nC Qgd Gate-drain charge VDD = 640 V, ID = 2 A, VGS = 10 V ( see Figure 15: "Test circuit for gate charge behavior" ) - 1.53 - nC Notes: (1)Time related is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDSS (2)Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 4/15 DocID027714 Rev 2 STD3LN80K5 Electrical characteristics Table 7: Switching times Symbol td(on) Parameter Turn-on delay time tr Rise time td(off) Turn-off delay time tf Fall time Test conditions Min. Typ. Max. Unit VDD = 400 V, ID = 1 A, RG = 4.7 Ω, VGS = 10 V ( see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform" ) - 6.2 - ns - 7 - ns - 30 - ns - 26 - ns Min. Typ. Max. Unit Table 8: Source drain diode Symbol Parameter Test conditions ISD Source-drain current - 2 A ISDM(1) Source-drain current (pulsed) - 8 A VSD(2) Forward on voltage ISD = 2 A, VGS = 0 V trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current - 1.5 V - 210 ns - 0.8 µC - 7.6 A - 345 ns - 1.2 µC - 7.2 A Test conditions Min. Typ. Max. Unit IGS = ± 1 mA, ID = 0 A 30 - - V ISD = 2 A, di/dt = 100 A/µs, VDD = 60 V ( see Figure 16: "Test circuit for inductive load switching and diode recovery times" ) ISD = 2 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C, (see Figure 16: "Test circuit for inductive load switching and diode recovery times" ) Notes: (1)Pulse width limited by safe operating area. (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5%. Table 9: Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DocID027714 Rev 2 5/15 Electrical characteristics 2.1 STD3LN80K5 Electrical characteristics (curves) Figure 3: Thermal impedance Figure 2: Safe operating area CG34360 K 0 10 c -1 10 -2 10 -5 10 Figure 4: Output characteristics Figure 6: Gate charge vs gate-source voltage 6/15 -4 10 -3 10 -2 10 -1 10 tp (s) Figure 5: Transfer characteristics Figure 7: Static drain-source on-resistance DocID027714 Rev 2 STD3LN80K5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Source-drain diode forward characteristics Figure 10: Normalized gate threshold voltage vs temperature Figure 11: Normalized on-resistance vs temperature Figure 12: Normalized V(BR)DSS vs temperature Figure 13: Maximum avalanche energy vs starting TJ DocID027714 Rev 2 7/15 Test circuits 3 STD3LN80K5 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior VDD RL IG= CONST VGS + pulse width 2200 μF 100 Ω D.U.T. 2.7 kΩ VG 47 kΩ 1 kΩ AM01469v10 Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform 8/15 DocID027714 Rev 2 Figure 19: Switching time waveform STD3LN80K5 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 DPAK package information Figure 20: DPAK (TO-252) type A package outline 0068772_A_21 DocID027714 Rev 2 9/15 Package information STD3LN80K5 Table 10: DPAK (TO-252) type A mechanical data mm Dim. Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 4.60 4.70 4.80 e 2.16 2.28 2.40 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 (L1) 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 10/15 Typ. 5.10 5.25 6.60 1.00 0.20 0° DocID027714 Rev 2 8° STD3LN80K5 Package information Figure 21: DPAK (TO-252) recommended footprint (dimensions are in mm) DocID027714 Rev 2 11/15 Package information 4.2 STD3LN80K5 DPAK packing information Figure 22: DPAK (TO-252) tape outline 12/15 DocID027714 Rev 2 STD3LN80K5 Package information Figure 23: DPAK (TO-252) reel outline Table 11: DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 B1 D 1.5 D1 1.5 E 1.65 F 1.6 Min. Max. 330 13.2 D 20.2 G 16.4 1.85 N 50 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 DocID027714 Rev 2 18.4 22.4 13/15 Revision history 5 STD3LN80K5 Revision history Table 12: Document revision history Date Revision 13-May-2015 1 Initial release 2 Updated title and features in cover page. Updated Section 1: "Electrical ratings" and Section 2: "Electrical characteristics". Added Section 2.1: "Electrical characteristics (curves)". Document status promoted from preliminary to production data. Minor text changes. 27-Jul-2016 14/15 Changes DocID027714 Rev 2 STD3LN80K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID027714 Rev 2 15/15