STD3N95K5AG

STD3N95K5AG Datasheet Automotive-grade N-channel 950 V, 4.3 Ω typ., 2 A MDmesh K5 Power MOSFET in a DPAK package Features TAB 2 3 1 DPAK D(2, TAB) G(1) Order code VDS RDS(on)max. ID PTOT STD3N95K5AG 950 V 5.0 Ω 2A 45 W • • AEC-Q101 qualified Industry’s lowest RDS(on) x area • • • • Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Applications S(3) AM01476v1_tab • Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Product status link STD3N95K5AG Product summary(1) Order code STD3N95K5AG Marking 3N95K5 Package DPAK Packing Tape and reel 1. The HTRB test was performed at 80% V(BR)DSS in compliance with AECQ101 rev. C. All the other tests were performed according to rev. D. DS12161 - Rev 2 - February 2021 For further information contact your local STMicroelectronics sales office. www.st.com STD3N95K5AG Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit ±30 V Drain current (continuous) at TC = 25 °C 2 A Drain current (continuous) at TC = 100 °C 1.3 A Drain current pulsed 3 A Total power dissipation at TC = 25 °C 45 W dv/dt (2) Peak diode recovery voltage slope 4.5 V/ns dv/dt (3) MOSFET dv/dt ruggedness 50 V/ns -55 to 150 °C Value Unit Thermal resistance, junction-to-case 2.78 °C/W Thermal resistance, junction-to-board 50 °C/W Value Unit VGS ID ID IDM (1) PTOT Tj Parameter Gate-source voltage Operating junction temperature range Tstg Storage temperature range 1. Pulse width limited by safe operating area. 2. ISD ≤ 2 A, di/dt ≤ 100 A/μs, VDS (peak) ≤ V(BR)DSS 3. VDS ≤ 760 V Table 2. Thermal data Symbol RthJC RthJB (1) Parameter 1. When mounted on 1 inch² FR-4, 2 Oz copper board Table 3. Avalanche characteristics Symbol DS12161 - Rev 2 Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by TJ max.) 1 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR, VDD = 50 V) 50 mJ page 2/15 STD3N95K5AG Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified Table 4. On/off-state Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. 950 1 µA 50 µA ±10 µA 4 5 V 4.3 5.0 Ω Min. Typ. Max. Unit - 105 - pF - 9 - pF - 0.8 - pF - 16 - pF 6 - pF VDS = 950 V, VGS = 0 V Zero gate voltage drain current TC = 125 °C (1) IGSS Gate body leakage current VGS = ±20 V, VDS = 0 V VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 1 A Unit V VDS = 950 V, VGS = 0 V IDSS Max. 3 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr) (1) Equivalent capacitance time related Co(er) (2) Equivalent capacitance energy related Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V VGS = 0 V, VDS = 0 to 760 V Rg Intrinsic gate resistance f = 1 MHz open drain - 16 - Ω Qg Total gate charge VDD = 760 V, ID = 2 A - 3.4 - nC Qgs Gate-source charge VGS= 0 to 10 V - 0.9 - nC Gate-drain charge (see Figure 14. Test circuit for gate charge behavior ) - 2.2 - nC Qgd 1. Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 2. Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS Table 6. Switching times Symbol td(on) tr td(off) tf DS12161 - Rev 2 Parameter Test conditions Min. Typ. Max. Unit Turn-on delay time VDD= 475 V, ID = 1 A, RG = 4.7 Ω - 8.5 - ns Rise time VGS = 10 V - 13.5 - ns Turn-off delay time (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) - 20.5 - ns - 32.5 - ns Fall time page 3/15 STD3N95K5AG Electrical characteristics Table 7. Source-drain diode Symbol ISD ISDM (1) VSD (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 2 A Source-drain current (pulsed) - 3 A 1.5 V Forward on voltage ISD = 2 A, VGS = 0 V - trr Reverse recovery time ISD = 2 A, di/dt = 100 A/µs, - 300 ns Qrr Reverse recovery charge VDD = 60 V - 1.15 µC IRRM Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times ) - 7.6 A trr Reverse recovery time ISD = 2 A, di/dt = 100 A/µs, - 525 ns Qrr Reverse recovery charge VDD = 60 V, TJ = 150 °C - 1.90 µC Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 7.2 A Min Typ. Max Unit ±30 - - V IRRM 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 8. Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS = ±1 mA, ID = 0 A The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DS12161 - Rev 2 page 4/15 STD3N95K5AG Electrical characteristics curves 2.1 Electrical characteristics curves Figure 2. Thermal impedance Figure 1. Safe operating area ID (A) GIPG250520171203SOA Operation in this area is limited by R DS(on) tp =10 µs 10 10 10 0 tp =100 µs -1 T j ≤150 °C T c = 25°C single pulse tp =1 ms tp =10 ms VDS (V) -2 10 10 -1 10 0 10 1 10 2 3 Figure 3. Output characteristics ID (A) Figure 4. Transfer characteristics ID (A) GIPG250520171204OCH 3.0 GIPG250520171208TCH VGS =9, 10 V 3 2.5 VDS = 20 V 2.0 2 1.5 VGS =8 V 1.0 1 VGS =7 V 0.5 VGS =6 V 0.0 0 5 10 15 20 VDS (V) Figure 5. Gate charge vs gate-source voltage VGS (V) GIPG250520171209QVG VDS (V) VDD = 760 V ID = 2 A 12 10 900 VDS 750 8 600 6 450 0 4 5 6 7 8 9 VGS (V) Figure 6. Static drain-source on-resistance RDS(on) (Ω) 5.5 GIPG250520171326RID VGS =10 V 5.0 4.5 Qgd 4 300 Qgs 2 0 0 DS12161 - Rev 2 150 0.5 1 1.5 2 2.5 3 3.5 0 Qg (nC) 4.0 3.5 3.0 0.0 0.5 1.0 1.5 2.0 ID (A) page 5/15 STD3N95K5AG Electrical characteristics curves Figure 7. Capacitance variations C (pF) 10 3 10 2 10 1 Figure 8. Output capacitance stored energy GIPD250920131533FSR E (µJ) GIPG250520171431CVR 3 CISS 2 COSS 10 10 0 CRSS 1 VDS (V) 0 0 f = 1 MHz -1 10 -1 10 10 0 1 10 2 Figure 9. Normalized gate threshold voltage vs temperature GIPD250920131539FSR VGS(th) (norm) 1.2 200 400 600 800 VDS(V) Figure 10. Normalized V(BR)DSS vs temperature GIPD250920131550FSR V(BR)DSS (norm) 1.1 ID= 1mA 1.05 1 1 0.8 0.95 0.6 0.4 -100 0.9 -50 0 50 100 150 Tj(°C) Figure 11. Normalized on-resistance vs temperature GIPD250920131545FSR RDS(on) (norm) 2.5 0.85 -100 VSD (V) 0.9 1.5 0.8 1 0.7 0.5 0.6 DS12161 - Rev 2 -50 0 50 100 150 Tj(°C) 100 50 150 Tj(°C) GIPG250520171323SDF Tj = -50 °C 1.0 ID= 1A VGS= 10V 0 Figure 12. Source-drain diode forward characteristics 2 0 -100 -50 0.5 0 Tj = 25 °C Tj = 150 °C 0.5 1.0 1.5 2.0 ISD (A) page 6/15 STD3N95K5AG Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD RL RL 2200 + μF 3.3 μF VDD RG VGS IG= CONST VGS VD + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v10 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times Figure 16. Unclamped inductive load test circuit D G A D.U.T. S 25 Ω A A B B B G RG VD 3.3 µF D + L 100 µH fast diode 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi pulse width _ AM01471v1 AM01470v1 Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform V(BR)DSS ton td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD VGS 0 VDS 10% 90% 10% AM01473v1 AM01472v1 DS12161 - Rev 2 page 7/15 STD3N95K5AG Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 DPAK (TO-252) package information Figure 19. DPAK (TO-252) type A package outline 0068772_A_30 DS12161 - Rev 2 page 8/15 STD3N95K5AG DPAK (TO-252) package information Table 9. DPAK (TO-252) type A mechanical data Dim. mm Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 4.60 4.70 4.80 e 2.159 2.286 2.413 e1 4.445 4.572 4.699 H 9.35 10.10 L 1.00 1.50 (L1) 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 DS12161 - Rev 2 Typ. 5.10 5.25 6.60 1.00 0.20 0° 8° page 9/15 STD3N95K5AG DPAK (TO-252) package information Figure 20. DPAK (TO-252) recommended footprint (dimensions are in mm) FP_0068772_30 DS12161 - Rev 2 page 10/15 STD3N95K5AG DPAK (TO-252) package information 4.1.1 DPAK (TO-252) packing information Figure 21. DPAK (TO-252) tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 K0 For machine ref. only including draft and radii concentric around B0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 DS12161 - Rev 2 page 11/15 STD3N95K5AG DPAK (TO-252) package information Figure 22. DPAK (TO-252) reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 10. DPAK (TO-252) tape and reel mechanical data Tape Dim. mm mm Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 DS12161 - Rev 2 Reel Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 18.4 22.4 page 12/15 STD3N95K5AG Revision history Table 11. Document revision history DS12161 - Rev 2 Date Revision Changes 06-Jun-2017 1 First release. 24-Feb-2021 2 Updated Section 4.1 DPAK (TO-252) package information. page 13/15 STD3N95K5AG Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 DPAK (TO-252) package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1.1 DPAK (TO-252) packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DS12161 - Rev 2 page 14/15 STD3N95K5AG IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2021 STMicroelectronics – All rights reserved DS12161 - Rev 2 page 15/15