STD3NC50

® STD3NC50 N - CHANNEL 500V - 2.4Ω - 3A TO-251/TO-252 PowerMESH™ ΙΙ MOSFET PRELIMINARY DATA TYPE ST D3NC50 s s s s s s V DSS 500 V R DS(on) < 2.7 Ω ID 3A TYPICAL RDS(on) = 2.4 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED NEW HIGH VOLTAGE BENCHMARK GATE CHARGE MINIMIZED ADD SUFFIX ”T4” FOR ORDERING IN TAPE & REEL. 3 1 DPAK TO-252 (Suffix ”T4”) IPAK TO-251 (Suffix ”-1”) 3 2 1 DESCRIPTION The PowerMESH™ ΙΙ is the evolution of the first generation of MESH OVERLAY™ . The layout refinements introduced greatly improve the Ron*area figure of merit while keeping the device at the leading edge for what concerns switching speed, gate charge and ruggedness. APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s SWITH MODE POWER SUPPLIES (SMPS) s DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVER INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol V DS V DGR V GS ID ID I DM ( • ) P tot dv/dt( 1 ) Ts tg Tj Parameter Drain-source Voltage (V GS = 0) Drain- gate Voltage (R GS = 20 k Ω ) G ate-source Voltage Drain Current (continuous) at Tc = 25 o C Drain Current (continuous) at Tc = 100 oC Drain Current (pulsed) T otal Dissipation at Tc = 25 C Derating Factor Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature o Value 500 500 ± 30 3.2 2 12.8 60 0.48 4 -65 to 150 150 ( 1) ISD ≤ 3 A, di/dt ≤ 100 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX Un it V V V A A A W W /o C V/ns o o C C (•) Pulse width limited by safe operating area January 2000 1/7 STD3NC50 THERMAL DATA R thj -case Rthj -amb R thc-sink Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature For Soldering Purpose 2.0 100 1.5 275 C/W oC/W o C/W o C o AVALANCHE CHARACTERISTICS Symbo l IAR E AS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy o (starting Tj = 25 C, I D = IAR , VDD = 50 V) Max Valu e 3 40 Unit A mJ ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symbo l V (BR)DSS I DSS IGSS Parameter Drain-source Breakdown Voltage Test Con ditions I D = 250 µ A V GS = 0 Min. 500 1 50 ± 100 T yp. Max. Unit V µA µA nA V DS = Max Rating Zero G ate Voltage Drain Current (V GS = 0) V DS = Max Rating Gate-body Leakage Current (VDS = 0) V GS = ± 30 V T c = 125 oC ON (∗) Symbo l V GS(th) R DS(on) I D(o n) Parameter Gate Threshold Voltage V DS = V GS Test Con ditions ID = 250 µ A ID = 1.5 A 3 Min. 2 T yp. 3 2.4 Max. 4 2.7 Unit V Ω A Static Drain-source O n V GS = 10V Resistance On State Drain Current V DS > ID(o n) x R DS(on )ma x V GS = 10 V DYNAMIC Symbo l g f s (∗ ) C iss C os s C rss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse T ransfer Capacitance Test Con ditions V DS > ID(o n) x R DS(on )ma x V DS = 25 V f = 1 MHz I D = 1.5 A V GS = 0 Min. T yp. 2 400 62 7.5 Max. Unit S pF pF pF 2/7 STD3NC50 ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbo l t d(on) tr Qg Q gs Q gd Parameter Turn-on Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Con ditions V DD = 300 V R G = 4.7 Ω V DD = 480 V ID = 1.5 A VGS = 10 V I D = 3 A V GS = 10 V Min. T yp. 11 8 15 6.5 5 21 Max. Unit ns ns nC nC nC SWITCHING OFF Symbo l tr (Voff) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Con ditions V DD = 400 V ID = 3 A R G = 4.7 Ω V GS = 10 V Min. T yp. 8 5 14 Max. Unit ns ns ns SOURCE DRAIN DIODE Symbo l ISD I SDM (• ) V SD ( ∗ ) t rr Q rr I RRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 3 A V GS = 0 245 980 8 I SD = 3 A di/dt = 100 A/ µ s T j = 150 o C V DD = 100 V Test Con ditions Min. T yp. Max. 3 12 1.6 Unit A A V ns µC A (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area 3/7 STD3NC50 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 4/7 STD3NC50 TO-251 (IPAK) MECHANICAL DATA DIM. MIN. A A1 A3 B B2 B3 B5 B6 C C2 D E G H L L1 L2 0.45 0.48 6 6.4 4.4 15.9 9 0.8 0.8 0.3 0.95 0.6 0.6 6.2 6.6 4.6 16.3 9.4 1.2 1 0.017 0.019 0.236 0.252 0.173 0.626 0.354 0.031 0.031 2.2 0.9 0.7 0.64 5.2 mm TYP. MAX. 2.4 1.1 1.3 0.9 5.4 0.85 0.012 0.037 0.023 0.023 0.244 0.260 0.181 0.641 0.370 0.047 0.039 MIN. 0.086 0.035 0.027 0.025 0.204 inch TYP. MAX. 0.094 0.043 0.051 0.031 0.212 0.033 H C A C2 L2 D B3 B6 A1 L = = 3 B5 B A3 = B2 = G = E L1 1 2 = 0068771-E 5/7 STD3NC50 TO-252 (DPAK) MECHANICAL DATA mm MIN. A A1 A2 B B2 C C2 D E G H L2 L4 0.6 2.2 0.9 0.03 0.64 5.2 0.45 0.48 6 6.4 4.4 9.35 0.8 1 0.023 TYP. MAX. 2.4 1.1 0.23 0.9 5.4 0.6 0.6 6.2 6.6 4.6 10.1 MIN. 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 0.252 0.173 0.368 0.031 0.039 inch TYP. MAX. 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 0.260 0.181 0.397 DIM. H A C2 C DETAIL ”A” A1 L2 D DETAIL ”A” B = = 3 B2 = = G E 2 L4 1 = = A2 0068772-B 6/7 STD3NC50 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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