STD40NF10

STD40NF10 Datasheet N-channel 100 V, 25 mΩ typ., 50 A, STripFET™ II Power MOSFET in a DPAK package Features TAB 2 3 1 • • • DPAK Type VDS RDS(on) max. ID STD40NF10 100 V 28 mΩ 50 A Exceptional dv/dt capability 100% avalanche tested Low gate charge D(2, TAB) Applications • G(1) Switching applications Description S(3) AM01475v1_noZen This Power MOSFET series has been developed using STMicroelectronics' unique STripFET™ process, which is specifically designed to minimize input capacitance and gate charge. This renders the device suitable for use as primary switch in advanced high-efficiency isolated DC-DC converters for telecom and computer applications, and applications with low gate charge driving requirements. Product status link STD40NF10 Product summary Order code STD40NF10 Marking D40NF10 Package DPAK Packing Tape and reel DS7037 - Rev 2 - August 2018 For further information contact your local STMicroelectronics sales office. www.st.com STD40NF10 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 100 V VGS Gate-source voltage ±20 V Drain current (continuous) at TC = 25 °C 50 A Drain current (continuous) at TC = 100 °C 35 A Drain current (pulsed) 200 A PTOT Total dissipation at TC = 25 °C 125 W EAS(3) Single-pulse avalanche energy 385 mJ dv/dt(4) Peak diode recovery voltage slope 27 V/ns -55 to 175 °C Value Unit ID(1) IDM (2) Tstg Tj Storage temperature range Operating junction temperature range 1. This value is limited by wire bonding. 2. Pulse width limited by safe operating area. 3. Starting TJ = 25 °C, ID = 50 A, VDD = 25 V 4. ISD ≤ 50 A, di/dt ≤ 600 A/μs, VDS ≤ V(BR)DSS, TJ ≤ TJMAX Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 1.2 °C/W Rthj-pcb(1) Thermal resistance junction-pcb 50 °C/W 1. When mounted on an FR-4 board of 1 inch², 2 oz Cu. DS7037 - Rev 2 page 2/18 STD40NF10 Electrical characteristics 2 Electrical characteristics TCASE = 25 °C unless otherwise specified Table 3. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 250 μA Min. Typ. 100 Zero gate voltage drain current 1 µA 10 µA ±100 nA 3 4 V 25 28 mΩ Min. Typ. Max. Unit - 2180 pF - 298 pF - 83.7 pF VGS = 0 V, VDS = 100 V, TC = 125 °C(1) IGSS Gate body leakage current VDS = 0 V, VGS = ±20 V VGS(th) Gate threshold voltage VDD = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 25 A Unit V VGS = 0 V, VDS = 100 V IDSS Max. 2 1. Defined by design, not subject to production test. Table 4. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge VDD = 50 V, ID = 40 A, - 46.5 Gate-source charge VGS = 0 to 10 V - 9 Gate-drain charge (see Figure 13. Test circuit for gate charge behavior) - 19 25 nC Min. Typ. Max. Unit Qgs Qgd VDS = 25 V, f = 1 MHz, VGS = 0 V 62 nC nC Table 5. Switching times Symbol td(on) tr td(off) tf Parameter Test conditions Turn-on delay time VDD = 50 V, ID = 25 A, - 21 - ns Rise time RG = 4.7 Ω, VGS = 10 V - 46 - ns Turn-off delay time (see Figure 12. Test circuit for resistive load switching times and Figure 17. Switching time waveform) - 54 - ns - 13 - ns Min. Typ. Max. Unit Fall time Table 6. Source-drain diode Symbol ISD ISDM(1) VSD DS7037 - Rev 2 (2) Parameter Test conditions Source-drain current - 50 A Source-drain current (pulsed) - 200 A - 1.5 V Forward on voltage ISD = 50 A, VGS = 0 V page 3/18 STD40NF10 Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit trr Reverse recovery time ISD = 50 A, di/dt = 100 A/µs, - 80 ns Qrr Reverse recovery charge VDD = 25 V, TJ = 150 °C - 250 nC Reverse recovery current (see Figure 14. Test circuit for inductive load switching and diode recovery times) - 6.4 A IRRM 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DS7037 - Rev 2 page 4/18 STD40NF10 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characteristics Figure 4. Transfer characteristics Figure 5. Static drain-source on-resistance Figure 6. Gate charge vs gate-source voltage DS7037 - Rev 2 page 5/18 STD40NF10 Electrical characteristics (curves) Figure 7. Capacitance variations Figure 8. Normalized gate threshold voltage vs temperature -100 Figure 9. Normalized on-resistance vs temperature Figure 10. Source-drain diode forward characteristics -100 Figure 11. Normalized V(BR)DSS vs temperature V(BR)DSS (norm.) -100 DS7037 - Rev 2 TJ (°C) page 6/18 STD40NF10 Test circuits 3 Test circuits Figure 12. Test circuit for resistive load switching times Figure 13. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 14. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 15. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 17. Switching time waveform Figure 16. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS7037 - Rev 2 page 7/18 STD40NF10 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS7037 - Rev 2 page 8/18 STD40NF10 DPAK (TO-252) type A2 package information 4.1 DPAK (TO-252) type A2 package information Figure 18. DPAK (TO-252) type A2 package outline 0068772_type-A2_rev25 DS7037 - Rev 2 page 9/18 STD40NF10 DPAK (TO-252) type A2 package information Table 7. DPAK (TO-252) type A2 mechanical data Dim. mm Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 5.10 5.20 5.30 e 2.159 2.286 2.413 e1 4.445 4.572 4.699 H 9.35 10.10 L 1.00 1.50 L1 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 DS7037 - Rev 2 Typ. 5.10 5.25 6.60 1.00 0.20 0° 8° page 10/18 STD40NF10 DPAK (TO-252) type C2 package information 4.2 DPAK (TO-252) type C2 package information Figure 19. DPAK (TO-252) type C2 package outline 0068772_C2_25 DS7037 - Rev 2 page 11/18 STD40NF10 DPAK (TO-252) type C2 package information Table 8. DPAK (TO-252) type C2 mechanical data Dim. mm Min. Typ. Max. A 2.20 2.30 2.38 A1 0.90 1.01 1.10 A2 0.00 0.10 b 0.72 0.85 b4 5.13 c 0.47 0.60 c2 0.47 0.60 D 6.00 D1 5.10 E 6.50 E1 5.20 e 2.186 2.286 2.386 H 9.80 10.10 10.40 L 1.40 1.50 1.70 L1 L2 6.20 5.60 6.60 6.70 5.50 0.90 1.25 0.51 BSC 0.60 L6 DS7037 - Rev 2 6.10 5.46 2.90 REF L3 L4 5.33 0.80 1.00 1.80 BSC θ1 5° 7° 9° θ2 5° 7° 9° V2 0° 8° page 12/18 STD40NF10 DPAK (TO-252) type C2 package information Figure 20. DPAK (TO-252) recommended footprint (dimensions are in mm) FP_0068772_25 DS7037 - Rev 2 page 13/18 STD40NF10 DPAK (TO-252) packing information 4.3 DPAK (TO-252) packing information Figure 21. DPAK (TO-252) tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 K0 For machine ref. only including draft and radii concentric around B0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 DS7037 - Rev 2 page 14/18 STD40NF10 DPAK (TO-252) packing information Figure 22. DPAK (TO-252) reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 9. DPAK (TO-252) tape and reel mechanical data Tape Dim. mm mm Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 DS7037 - Rev 2 Reel Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 18.4 22.4 page 15/18 STD40NF10 Revision history Table 10. Document revision history Date Version 19-Nov-2010 1 Changes First issue. Updated Section 2 Electrical characteristics. 09-Aug-2018 2 Updated Section 4 Package information. Minor text changes DS7037 - Rev 2 page 16/18 STD40NF10 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 DPAK (TO-252) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 DPAK (TO-252) type C2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 DS7037 - Rev 2 page 17/18 STD40NF10 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS7037 - Rev 2 page 18/18