STD45NF75T4
Datasheet
Automotive-grade N-channel 75 V, 18 mΩ, 40 A, STripFET™ II
Power MOSFET in a DPAK package
Features
TAB
2 3
1
DPAK
•
•
•
•
D(2, TAB)
Type
VDS
RDS(on) max.
ID
STD45NF75T4
75 V
24 mΩ
40 A
AEC-Q101 qualified
Exceptional dv/dt capability
100% avalanche tested
Low gate charge
Applications
G(1)
•
Switching applications
Description
S(3)
AM01475v1_noZen
This Power MOSFET series has been developed using STMicroelectronics' unique
STripFET™ process, which is specifically designed to minimize input capacitance
and gate charge. This renders the device suitable for use as primary switch in
advanced high-efficiency isolated DC-DC converters for telecom and computer
applications, and applications with low gate charge driving requirements.
Product status link
STD45NF75T4
Product summary
Order code
STD45NF75T4
Marking
D45NF75
Package
DPAK
Packing
Tape and reel
DS3559 - Rev 6 - October 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
STD45NF75T4
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDS
Drain-source voltage
75
V
VGS
Gate-source voltage
±20
V
Drain current (continuous) at TC = 25 °C
40(1)
A
Drain current (continuous) at TC = 100 °C
30
A
Drain current (pulsed)
160
A
PTOT
Total dissipation at TC = 25 °C
125
W
EAS(3)
Single-pulse avalanche energy
500
mJ
dv/dt(4)
Peak diode recovery voltage slope
20
V/ns
-55 to 175
°C
Value
Unit
ID
IDM
(2)
Tstg
Tj
Storage temperature range
Operating junction temperature range
1. This value is limited by package.
2. Pulse width is limited by safe operating area.
3. Starting TJ = 25 °C, ID = 20 A, VDD = 40 V
4. ISD ≤ 40 A, di/dt ≤ 800 A/μs, VDD ≤ V(BR)DSS, TJ ≤ TJMAX
Table 2. Thermal data
Symbol
Parameter
Rthj-case
Thermal resistance junction-case
1.2
°C/W
Rthj-pcb
Thermal resistance junction-pcb(1)
50
°C/W
1. When mounted on an 1-inch² FR-4, 2 Oz copper board.
DS3559 - Rev 6
page 2/16
STD45NF75T4
Electrical characteristics
2
Electrical characteristics
TCASE = 25 °C unless otherwise specified
Table 3. On/off states
Symbol
V(BR)DSS
Parameter
Test conditions
Drain-source breakdown voltage
VGS = 0 V, ID = 250 μA
Min.
Typ.
75
Zero gate voltage drain current
1
µA
10
µA
±100
nA
4
V
18
24
mΩ
Min.
Typ.
Max.
Unit
-
1760
-
pF
-
360
-
pF
-
140
-
pF
VGS = 0 V, VDS = 75 V,
TC = 125 °C(1)
IGSS
Gate body leakage current
VDS = 0 V, VGS = ±20 V
VGS(th)
Gate threshold voltage
VDD = VGS, ID = 250 µA
RDS(on)
Static drain-source on-resistance
VGS = 10 V, ID = 20 A
Unit
V
VGS = 0 V, VDS = 75 V
IDSS
Max.
2
1. Defined by design, not subject to production test.
Table 4. Dynamic
Symbol
Parameter
Test conditions
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer capacitance
Qg
Total gate charge
VDD = 60 V, ID = 40 A,
-
60
80
nC
Gate-source charge
RG = 4.7 Ω, VGS = 0 to 10 V
-
13
-
nC
Gate-drain charge
(see Figure 13. Test circuit for gate
charge behavior)
-
23
-
nC
Min.
Typ.
Max.
Unit
Qgs
Qgd
VDS = 25 V, f = 1 MHz,
VGS = 0 V
Table 5. Switching times
Symbol
td(on)
tr
td(off)
tf
DS3559 - Rev 6
Parameter
Test conditions
Turn-on delay time
VDD = 37 V, ID = 20 A,
-
15
-
ns
Rise time
RG = 4.7 Ω, VGS = 10 V
-
40
-
ns
Turn-off delay time
(see Figure 12. Test circuit for
resistive load switching times and
Figure 17. Switching time
waveform)
-
55
-
ns
-
10
-
ns
Fall time
page 3/16
STD45NF75T4
Electrical characteristics
Table 6. Source-drain diode
Symbol
ISD
ISDM(1)
(2)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Source-drain current
-
40
A
Source-drain current (pulsed)
-
160
A
1.5
V
Forward on voltage
ISD = 40 A, VGS = 0 V
-
trr
Reverse recovery time
ISD = 40 A, di/dt = 100 A/µs,
-
120
ns
Qrr
Reverse recovery charge
VDD = 30 V, TJ = 150 °C
-
410
nC
Reverse recovery current
(see Figure 17. Switching time
waveform)
-
7.5
A
VSD
IRRM
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
DS3559 - Rev 6
page 4/16
STD45NF75T4
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
Figure 2. Thermal impedance
Figure 1. Safe operating area
AM03943v1
ID
(A)
280dpg
K
δ=0.5
is
e a n)
ar
is DS (o
h
t
in a x R
n
tio y m
b
ra
e
d
O p ite
Lim
100
10
0.2
100µs
-1
0.05
1ms
Tj=175°C
Tc=25°C
1
0.1
10
0.01
Single
puls e
0.1
0.1
-2
1
10
Zth=k Rthj-c
δ=tp/τ
0.02
10ms
VDS (V)
Figure 3. Output characteristics
10 -5
10
S ingle puls e
10
-4
tp
τ
10
-3
10
-2
10
-1
tp (s )
Figure 4. Transfer characteristics
VDS = 10 V
Figure 5. Static drain-source on-resistance
DS3559 - Rev 6
Figure 6. Gate charge vs gate-source voltage
page 5/16
STD45NF75T4
Electrical characteristics (curves)
Figure 8. Normalized gate threshold voltage vs
temperature
Figure 7. Capacitance variations
-75
Figure 9. Normalized on-resistance vs temperature
-75
-25
25
75
125
175
-25
25
75
125
175
TJ (°C)
Figure 10. Source-drain diode forward characteristics
TJ (°C)
Figure 11. Normalized V(BR)DSS vs temperature
VGS = 0 V,
ID = 250 μA
-75
DS3559 - Rev 6
-25
25
75
125
175
TJ (°C)
page 6/16
STD45NF75T4
Test circuits
3
Test circuits
Figure 12. Test circuit for resistive load switching times
Figure 13. Test circuit for gate charge behavior
VDD
12 V
2200
+ μF
3.3
μF
VDD
VD
VGS
1 kΩ
100 nF
RL
IG= CONST
VGS
RG
47 kΩ
+
pulse width
D.U.T.
2.7 kΩ
2200
μF
pulse width
D.U.T.
100 Ω
VG
47 kΩ
1 kΩ
AM01469v1
AM01468v1
Figure 14. Test circuit for inductive load switching and
diode recovery times
D
G
A
D.U.T.
S
25 Ω
A
L
A
B
B
3.3
µF
D
G
+
VD
100 µH
fast
diode
B
Figure 15. Unclamped inductive load test circuit
RG
1000
+ µF
2200
+ µF
VDD
3.3
µF
VDD
ID
D.U.T.
S
D.U.T.
Vi
_
pulse width
AM01471v1
AM01470v1
Figure 17. Switching time waveform
Figure 16. Unclamped inductive waveform
ton
V(BR)DSS
td(on)
VD
toff
td(off)
tr
tf
90%
90%
IDM
VDD
10%
0
ID
VDD
AM01472v1
VGS
0
VDS
10%
90%
10%
AM01473v1
DS3559 - Rev 6
page 7/16
STD45NF75T4
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
DS3559 - Rev 6
page 8/16
STD45NF75T4
DPAK (TO-252) type A2 package information
4.1
DPAK (TO-252) type A2 package information
Figure 18. DPAK (TO-252) type A2 package outline
0068772_type-A2_rev25
DS3559 - Rev 6
page 9/16
STD45NF75T4
DPAK (TO-252) type A2 package information
Table 7. DPAK (TO-252) type A2 mechanical data
Dim.
mm
Min.
Max.
A
2.20
2.40
A1
0.90
1.10
A2
0.03
0.23
b
0.64
0.90
b4
5.20
5.40
c
0.45
0.60
c2
0.48
0.60
D
6.00
6.20
D1
4.95
E
6.40
E1
5.10
5.20
5.30
e
2.159
2.286
2.413
e1
4.445
4.572
4.699
H
9.35
10.10
L
1.00
1.50
L1
2.60
2.80
3.00
L2
0.65
0.80
0.95
L4
0.60
R
V2
DS3559 - Rev 6
Typ.
5.10
5.25
6.60
1.00
0.20
0°
8°
page 10/16
STD45NF75T4
DPAK (TO-252) type A2 package information
Figure 19. DPAK (TO-252) recommended footprint (dimensions are in mm)
FP_0068772_25
DS3559 - Rev 6
page 11/16
STD45NF75T4
DPAK (TO-252) packing information
4.2
DPAK (TO-252) packing information
Figure 20. DPAK (TO-252) tape outline
10 pitches cumulative
tolerance on tape +/- 0.2 mm
T
P0
Top cover
tape
P2
D
E
F
B1
K0
For machine ref. only
including draft and
radii concentric around B0
W
B0
A0
P1
D1
User direction of feed
R
Bending radius
User direction of feed
AM08852v1
DS3559 - Rev 6
page 12/16
STD45NF75T4
DPAK (TO-252) packing information
Figure 21. DPAK (TO-252) reel outline
T
40mm min.
access hole
at slot location
B
D
C
N
A
G measured
at hub
Tape slot
in core for
tape start
2.5mm min.width
Full radius
AM06038v1
Table 8. DPAK (TO-252) tape and reel mechanical data
Tape
Dim.
mm
mm
Dim.
Min.
Max.
A0
6.8
7
A
B0
10.4
10.6
B
1.5
12.1
C
12.8
1.6
D
20.2
G
16.4
50
B1
DS3559 - Rev 6
Reel
Min.
Max.
330
13.2
D
1.5
D1
1.5
E
1.65
1.85
N
F
7.4
7.6
T
K0
2.55
2.75
P0
3.9
4.1
Base qty.
2500
P1
7.9
8.1
Bulk qty.
2500
P2
1.9
2.1
R
40
T
0.25
0.35
W
15.7
16.3
18.4
22.4
page 13/16
STD45NF75T4
Revision history
Table 9. Document revision history
Date
Version
Changes
22-Jun-2004
1
Preliminary version
09-Sep-2004
2
Complete version
11-Jul-2006
3
New template, no content change
20-Feb-2007
4
Typo mistake on page 1
20-May-2009
5
Figure 2 and Figure 3 have been updated
Updated information on cover page.
03-Oct-2018
6
Updated Section 4 Package information.
Minor text changes
DS3559 - Rev 6
page 14/16
STD45NF75T4
Contents
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
DPAK (TO-252) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
DS3559 - Rev 6
page 15/16
STD45NF75T4
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS3559 - Rev 6
page 16/16