STD4N90K5

STD4N90K5 N-channel 900 V, 1.90 Ω typ.,3 A MDmesh™ K5 Power MOSFET in a DPAK package Datasheet - production data Features      Order code VDS RDS(on) max. ID STD4N90K5 900 V 2.10 Ω 3A Industry’s lowest RDS(on) x area Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Figure 1: Internal schematic diagram Applications  Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Table 1: Device summary Order code Marking Package Packing STD4N90K5 4N90K5 DPAK Tape and reel November 2016 DocID029956 Rev 1 This is information on a product in full production. 1/15 www.st.com Contents STD4N90K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/15 4.1 DPAK package information ............................................................... 9 4.2 DPAK packing information .............................................................. 12 Revision history ............................................................................ 14 DocID029956 Rev 1 STD4N90K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter VGS Gate-source voltage Value Unit ± 30 V ID Drain current (continuous) at TC = 25 °C 3 A ID Drain current (continuous) at TC = 100 °C 1.9 A Drain current (pulsed) 12 A W ID(1) PTOT Total dissipation at TC = 25 °C 60 dv/dt (2) Peak diode recovery voltage slope 4.5 dv/dt (3) MOSFET dv/dt ruggedness 50 Tj Operating junction temperature range Tstg Storage temperature range V/ns - 55 to 150 °C Notes: (1)Pulse (2)I SD (3)V width limited by safe operating area ≤ 3 A, di/dt ≤ 100 A/μs; VDS peak < V(BR)DSS, VDD = 450 V. DS ≤ 720 V Table 3: Thermal data Symbol Rthj-pcb (1) Rthj-amb Parameter Thermal resistance junction-pcb Thermal resistance junction-ambient Value Unit 50 °C/W 62.5 °C/W Notes: (1)When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 s. Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by T jmax) 1 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 160 mJ DocID029956 Rev 1 3/15 Electrical characteristics 2 STD4N90K5 Electrical characteristics TC = 25 °C unless otherwise specified Table 5: On/off-state Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions Min. VGS = 0 V, ID = 1 mA 900 Typ. Max. Unit V VGS = 0 V, VDS = 900 V 1 µA IDSS Zero gate voltage drain current VGS = 0 V, VDS = 900 V TC = 125 °C(1) 50 µA IGSS Gate body leakage current VDS = 0 V, VGS = ±20 V ±10 µA VGS(th) Gate threshold voltage VDD = VGS, ID = 100 µA 4 5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 1.5 A 1.90 2.10 Ω Min. Typ. Max. Unit - 173 - pF - 17.9 - pF - 1 - pF - 29 - pF - 11 - pF 3 Notes: (1) Defined by design, not subject to production test. Table 6: Dynamic Symbol Ciss Parameter Test conditions Input capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance Co(tr)(1) Equivalent capacitance time related Co(er)(2) Equivalent capacitance energy related VDS = 0 to 720 V, VGS = 0 V Rg Intrinsic gate resistance f = 1 MHz, ID = 0 A - 15.5 - Ω Qg Total gate charge - 5.3 - nC Qgs Gate-source charge - 1.45 - nC Qgd Gate-drain charge VDD = 720 V, ID = 3 A VGS= 10 V (see Figure 15: "Test circuit for gate charge behavior") - 2.8 - nC Notes: (1) Time related is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDSS. (2) Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS. 4/15 DocID029956 Rev 1 STD4N90K5 Electrical characteristics Table 7: Switching times Symbol td(on) Parameter Turn-on delay time tr Rise time td(off) Turn-off delay time tf Fall time Test conditions Min. Typ. Max. Unit VDD= 450 V, ID = 1.50 A, RG = 4.7 Ω VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") - 10.5 - ns - 11.8 - ns - 26.4 - ns - 25.5 - ns Min. Typ. Max. Unit Table 8: Source-drain diode Symbol Parameter Test conditions Source-drain current - 3 A ISDM(1) Source-drain current (pulsed) - 12 A VSD(2) Forward on voltage ISD = 3 A, VGS = 0 V - 1.5 V trr Reverse recovery time - 289 ns Qrr Reverse recovery charge - 1.56 µC IRRM Reverse recovery current ISD = 3 A, di/dt = 100 A/µs,VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 10.8 A ISD = 3 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 494 ns - 2.45 µC - 9.9 A Min. Typ. Max. Unit 30 - - V ISD trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1)Pulse width limited by safe operating area (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 9: Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS = ± 1 mA,ID = 0 A The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DocID029956 Rev 1 5/15 Electrical characteristics 2.1 STD4N90K5 Electrical characteristics (curves) Figure 3: Thermal impedance Figure 2: Safe operating area CG34360 K 0 10 c -1 10 -2 10 -5 10 -4 10 -3 10 -2 10 -1 10 tp (s) Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/15 DocID029956 Rev 1 STD4N90K5 Electrical characteristics Figure 8: Capacitance variations Figure 10: Normalized on-resistance vs temperature Figure 12: Maximum avalanche energy vs starting TJ Figure 9: Normalized gate threshold voltage vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 13: Source-drain diode forward characteristics DocID029956 Rev 1 7/15 Test circuits 3 STD4N90K5 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior VDD RL IG= CONST VGS + pulse width 2200 μF 100 Ω D.U.T. 2.7 kΩ VG 47 kΩ 1 kΩ AM01469v10 Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform 8/15 DocID029956 Rev 1 Figure 19: Switching time waveform STD4N90K5 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 DPAK package information Figure 20: DPAK (TO-252) type A package outline 0068772_A_21 DocID029956 Rev 1 9/15 Package information STD4N90K5 Table 10: DPAK (TO-252) type A mechanical data mm Dim. Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 4.60 4.70 4.80 e 2.16 2.28 2.40 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 (L1) 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 10/15 Typ. 5.10 5.25 6.60 1.00 0.20 0° DocID029956 Rev 1 8° STD4N90K5 Package information Figure 21: DPAK (TO-252) recommended footprint (dimensions are in mm) DocID029956 Rev 1 11/15 Package information 4.2 STD4N90K5 DPAK packing information Figure 22: DPAK (TO-252) tape outline 12/15 DocID029956 Rev 1 STD4N90K5 Package information Figure 23: DPAK (TO-252) reel outline Table 11: DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 B1 D 1.5 D1 1.5 E 1.65 F 1.6 Min. Max. 330 13.2 D 20.2 G 16.4 1.85 N 50 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 DocID029956 Rev 1 18.4 22.4 13/15 Revision history 5 STD4N90K5 Revision history Table 12: Document revision history 14/15 Date Revision 02-Nov-2016 1 DocID029956 Rev 1 Changes First release. STD4N90K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID029956 Rev 1 15/15