STD4NK100Z

STD4NK100Z Automotive-grade N-channel 1000 V, 5.6 Ω typ., 2.2 A SuperMESH™ Power MOSFET Zener-protected in a DPAK Datasheet - production data Features 7$%  Order code VDSS RDS(on)max ID STD4NK100Z 1000 V 6.8 Ω 2.2 A • Designed for automotive applications and AEC-Q101 qualified  • Extremely high dv/dt capability  • 100% avalanche tested • Gate charge minimized '3$. • Very low intrinsic capacitance • Zener-protected Figure 1. Internal schematic diagram '7$% Applications • Switching application Description * 6 $0YBWDE This device is an N-channel Zener-protected Power MOSFET developed using STMicroelectronics’ SuperMESH™ technology, achieved through optimization of ST’s well established strip-based PowerMESH™ layout. In addition to a significant reduction in onresistance, this device is designed to ensure a high level of dv/dt capability for the most demanding applications. Table 1. Device summary Order code Marking Package Packaging STD4NK100Z 4NK100Z DPAK Tape and reel Note: HTRB test has been performed at 80% of V(BR)DSS according to AEC-Q101 rev. C. All the other tests have been done according to the new rev. D. April 2015 This is information on a product in full production. DocID022821 Rev 2 1/16 www.st.com Contents STD4NK100Z Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 Test circuits 4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2/16 .............................................. 8 DocID022821 Rev 2 STD4NK100Z 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 1000 V VGS Gate-source voltage ± 30 V ID Drain current (continuous) at TC = 25 °C 2.2 A ID Drain current (continuous) at TC=100 °C 1 A IDM(1) Drain current (pulsed) 8.8 A PTOT Total dissipation at TC = 25 °C 90 W 3000 V 4.5 V/ns -55 to 150 °C Value Unit 1.39 °C/W 50 °C/W Value Unit VESD(G-S) Gate source ESD (HBM-C=100pF, R=1.5 kΩ) dv/dt (2) TJ Tstg Peak diode recovery voltage slope Operating junction temperature Storage temperature 1. Pulse width limited by safe operating area 2. ISD ≤ 2.2 A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. Table 3. Thermal data Symbol Rthj-case Parameter Thermal resistance junction-case max Rthj-pcb(1) Thermal resistance junction-pcb max 1. When mounted on 1inch² FR-4 board, 2 oz Cu Table 4. Avalanche characteristics Symbol Parameter IAR Avalanche current, repetitive or not-repetitive (pulse width limited by TJMAX) 2.2 A EAS Single pulse avalanche energy (starting TJ=25 °C, ID=IAR, VDD=50 V) 110 mJ DocID022821 Rev 2 3/16 16 Electrical characteristics 2 STD4NK100Z Electrical characteristics (TCASE=25 °C unless otherwise specified) Table 5. On/off states Symbol Parameter Test conditions Drain-source breakdown voltage ID = 1 mA, VGS= 0 IDSS Zero gate voltage drain current (VGS = 0) VDS = 1000 V, VDS = 1000 V, Tc = 125 °C IGSS Gate body leakage current VGS = ± 20 V (VGS = 0) V(BR)DSS VGS(th) Gate threshold voltage VDS = VGS, ID = 50 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 1.1 A Min. Typ. Max. Unit 1000 V 1 50 µA µA ±10 µA 3.75 4.5 V 5.6 6.8 Ω Min. Typ. Max. Unit - 601 - pF - 53 - pF - 12 - pF - 15 - pF - 15 - ns - 7.5 - ns - 32 - ns - 39 - ns - 18 - nC - 3.6 - nC - 9.2 - nC 3 Table 6. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss. eq(1) Equivalent output capacitance td(on) Turn-on delay time tr td(off) tf Rise time Off-voltage rise time Test conditions VDS =25 V, f=1 MHz, VGS=0 VGS=0, VDS =0 V to 800 V VDD=500 V, ID= 1.25 A, RG=4.7 Ω, VGS=10 V (see Figure 16) Fall time Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VDD=800 V, ID = 2.5 A VGS =10 V (see Figure 15) 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 4/16 DocID022821 Rev 2 STD4NK100Z Electrical characteristics Table 7. Source drain diode Symbol ISD ISDM(1) (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 2.2 A Source-drain current (pulsed) - 8.8 A 1.6 V Forward on voltage ISD= 2.2 A, VGS=0 - trr Reverse recovery time - 584 ns Qrr Reverse recovery charge - 2.3 µC IRRM Reverse recovery current ISD= 2.5 A, di/dt = 100 A/µs, VDD=100 V (see Figure 14) - 8 A - 628 ns - 2.5 µC - 8.1 A VSD trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD= 2.5 A, di/dt = 100 A/µs, VDD=100 V, Tj=150 °C (see Figure 14) 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300 µs, duty cycle 1.5% Table 8. Gate-source Zener diode Symbol Parameter Test conditions V(BR)GSO Gate-source breakdown voltage Igs=± 1 mA, ID=0 Min. 30 Typ. Max. - Unit V The built-in back-to-back Zener diodes have specifically been designed to enhance the device's ESD capability. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components. DocID022821 Rev 2 5/16 16 Electrical characteristics 2.1 STD4NK100Z Electrical characteristics (curves) Figure 2. Safe operating area *,3')65 ,' $   Q —V R 6 ' LV WK [5 D P \ E LQ Q WLR —V LV HD U D PV UD G SH LWH P /L 2  PV    Figure 3. Thermal impedance 7M ƒ& 7F ƒ& 6LQJOHSXOVH     9'69 Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Normalized V(BR)DSS vs. temperature Figure 7. Static drain-source on-resistance 6/16 DocID022821 Rev 2 STD4NK100Z Electrical characteristics Figure 8. Gate charge vs. gate-source voltage Figure 9. Capacitance variations Figure 10. Normalized gate threshold voltage vs. temperature Figure 11. Normalized on-resistance vs. temperature Figure 12. Source-drain diode forward characteristics Figure 13. Maximum avalanche energy vs Tj DocID022821 Rev 2 7/16 16 Test circuits 3 STD4NK100Z Test circuits Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF IG=CONST VDD VGS 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 Figure 16. Test circuit for inductive load switching and diode recovery times A A AM01469v1 Figure 17. Unclamped inductive load test circuit L A D G D.U.T. FAST DIODE B B VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 8/16 0 DocID022821 Rev 2 10% AM01473v1 STD4NK100Z 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DocID022821 Rev 2 9/16 16 Package information STD4NK100Z Figure 20. DPAK (TO-252) type A2 outline BW\SH$BUHY 10/16 DocID022821 Rev 2 STD4NK100Z Package information Table 9. DPAK (TO-252) type A2 mechanical data mm Dim. Min. Typ. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 5.10 5.20 5.30 e 2.16 2.28 2.40 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 L1 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 5.10 6.60 1.00 R V2 5.25 0.20 0° 8° DocID022821 Rev 2 11/16 16 Package information STD4NK100Z Figure 21. DPAK (TO-252) footprint (a) )3BB5 a. All dimensions are in millimeters 12/16 DocID022821 Rev 2 STD4NK100Z 5 Packing information Packing information Table 10. DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 DocID022821 Rev 2 18.4 22.4 13/16 16 Packing information STD4NK100Z Figure 22. Tape for DPAK (TO-252) 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 W K0 B0 For machine ref. only including draft and radii concentric around B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 Figure 23. Reel for DPAK (TO-252) T REEL DIMENSIONS 40mm min. Access hole At sl ot location B D C N A Full radius Tape slot in core for tape start 25 mm min. width G measured at hub AM08851v2 14/16 DocID022821 Rev 2 STD4NK100Z 6 Revision history Revision history Table 11. Document revision history Date Revision 01-Oct-2013 1 First release. 2 Document status promoted from preliminary to production data. Updated title and features in cover page. Updated Section 2.1: Electrical characteristics (curves) and Section 4: Package information. Minor text changes. 13-Apr-2015 Changes DocID022821 Rev 2 15/16 16 STD4NK100Z IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 16/16 DocID022821 Rev 2