STD5N20T4

STD5N20 N-CHANNEL 200V - 0.6Ω - 5A DPAK MESH OVERLAY™ MOSFET TYPE STD5N20 ■ ■ ■ ■ VDSS RDS(on) ID 200 V < 0.8 Ω 5A TYPICAL RDS(on) = 0.6 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED ADD SUFFIX “T4” FOR OREDERING IN TAPE & REEL 1 DESCRIPTION Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performance. The new patented STrip layout coupled with the Company’s proprietary edge termination structure, makes it suitable in coverters for lighting applications. ) (s ) s ( ct 3 u d o r P e DPAK TO-252 t e l o INTERNAL SCHEMATIC DIAGRAM s b O APPLICATIONS ■ HIGH CURRENT, HIGH SPEED SWITCHING ■ SWITH MODE POWER SUPPLIES (SMPS) ■ DC-DC CONVERTERS FOR TELECOM, INDUSTRIAL, AND LIGHTING EQUIPMENT t c u d o r P e t e l o ABSOLUTE MAXIMUM RATINGS s b O Symbol VDS VDGR VGS Value Unit Drain-source Voltage (VGS = 0) Parameter 200 V Drain-gate Voltage (RGS = 20 kΩ) 200 V Gate- source Voltage ±20 V ID Drain Current (continuous) at TC = 25°C 5 A ID Drain Current (continuous) at TC = 100°C 3.5 A Drain Current (pulsed) 20 A Total Dissipation at TC = 25°C 45 W 0.36 W/°C 5 V/ns –65 to 150 °C 150 °C IDM (l) PTOT Derating Factor dv/dt (1) Tstg Tj Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature (•)Pulse width limited by safe operating area December 2000 (1)ISD ≤5A, di/dt ≤300A/µs, V DD ≤ V(BR)DSS, Tj ≤ TJMAX. (**) Limited only by Maximum Temperature Allowed 1/8 STD5N20 THERMAL DATA Rthj-case Thermal Resistance Junction-case Max 2.77 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 100 °C/W Rthc-sink Thermal Resistance Case-sink Typ 1.5 °C/W Maximum Lead Temperature For Soldering Purpose 275 °C Tl AVALANCHE CHARACTERISTICS Symbol Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) Max Value Unit 5 A 130 mJ ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Test Conditions Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 ) (s Parameter Gate Threshold Voltage RDS(on) Static Drain-source On Resistance ID(on) On State Drain Current Test Conditions ct du e t e ol Pr s b O VGS = ±20V ON (1) VGS(th) Typ. VDS = Max Rating, TC = 125 °C Gate-body Leakage Current (VDS = 0) Symbol e t e ol VDS = Max Rating Zero Gate Voltage Drain Current (VGS = 0) u d o Min. 200 o r P VDS = VGS, ID = 250µA Max. Unit V 1 µA 50 µA ±100 nA Min. Typ. Max. Unit 2 3 4 V 0.7 0.8 Ω VGS = 10V, ID = 2.5 A VDS > ID(on) x RDS(on)max, VGS = 10V ) s ( ct 5 A DYNAMIC bs Symbol O 2/8 gfs (1) Parameter Forward Transconductance Test Conditions VDS > ID(on) x RDS(on)max, ID = 2.5A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. Max. Unit 1.5 4 S 350 pF Ciss Input Capacitance Coss Output Capacitance 70 pF Crss Reverse Transfer Capacitance 35 pF STD5N20 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Parameter Test Conditions Rise Time Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge Typ. VDD = 100 V, ID = 3 A RG = 4.7Ω VGS = 10 V (see test circuit, Figure 3) Turn-on Delay Time Qg Min. VDD = 160V, ID = 6 A, VGS = 10V Max. 18 ns 30 ns 19 27 tr(Voff) Parameter Test Conditions nC 7.5 nC 10 ) s ( ct tf Fall Time Cross-over Time 65 ns SOURCE DRAIN DIODE Symbol ISD Typ. VDD = 160V, ID = 6 A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 5) Off-voltage Rise Time tc Min. 40 t e l o Parameter Test Conditions Source-drain Current Source-drain Current (pulsed) VSD (1) Forward On Voltage ISD = 6 A, VGS = 0 trr Reverse Recovery Time Qrr Reverse Recovery Charge ISD =6 A, di/dt = 100A/µs VDD = 100V, Tj = 150°C (see test circuit, Figure 5) IRRM Reverse Recovery Current )- Min. s b O ISDM (2) t(s c u d Max. Typ. Unit ns u d o r P e nC 4.5 SWITCHING OFF Symbol Unit ns Max. Unit 6 A 24 A 1.5 V 155 ns 700 nC 9 A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. o r P Safe Operating Area e t e ol Thermal Impedance s b O 3/8 STD5N20 Output Characteristics Tranfer Characteristics ) s ( ct u d o r P e Tranconductance Static Drain-Source On Resistance t e l o ) (s s b O t c u d o r P e t e l o Gate Charge vs Gate-source Voltage s b O 4/8 Capacitance Variations STD5N20 Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature ) s ( ct u d o r P e Source-drain Diode Forward Characteristics t e l o ) (s s b O t c u d o r P e t e l o s b O 5/8 STD5N20 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform ) s ( ct u d o r P e Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit t e l o ) (s t c u d o r P e t e l o Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times s b O 6/8 s b O STD5N20 TO-252 (DPAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 2.20 2.40 0.087 0.094 A1 0.90 1.10 0.035 0.043 ) s ( ct A2 0.03 0.23 0.001 B 0.64 0.90 0.025 B2 5.20 5.40 0.204 C 0.45 0.60 0.018 C2 0.48 0.60 0.019 D 6.00 6.20 0.236 E 6.40 6.60 0.252 G 4.40 4.60 H 9.35 10.10 L2 0.8 L4 0.60 V2 0o )- 0.009 0.035 0.213 P e s b O t e l o 0.173 ro du 0.368 0.024 0.024 0.244 0.260 0.181 0.398 0.031 1.00 0.024 0.039 8o 0o 0o s ( t c u d o r P e t e l o s b O P032P_B 7/8 STD5N20 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 8/8