STD5N80K5

STD5N80K5 Datasheet N-channel 800 V, 1.50 Ω typ., 4 A MDmesh K5 Power MOSFET in a DPAK package Features TAB 2 3 1 DPAK D(2, TAB) Order code VDS RDS(on) max. ID STD5N80K5 800 V 1.75 Ω 4A • Industry’s lowest RDS(on) x area • • • • Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Applications G(1) • S(3) AM01475V1 Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Product status link STD5N80K5 Product summary Order code STD5N80K5 Marking 5N80K5 Package DPAK Packing Tape and reel DS11344 - Rev 4 - July 2019 For further information contact your local STMicroelectronics sales office. www.st.com STD5N80K5 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ±30 V ID Drain current (continuous) at TC = 25 °C 4 A ID Drain current (continuous) at TC = 100 °C 2.3 A Drain current (pulsed) 16 A Total power dissipation at TC = 25 °C 60 W Peak diode recovery voltage slope 4.5 MOSFET dv/dt ruggedness 50 IDM (1) PTOT dv/dt (2) dv/dt (3) TJ Tstg Operating junction temperature range Storage temperature range V/ns - 55 to 150 °C Value Unit 1. Pulse width limited by safe operating area. 2. ISD ≤ 4 A, di/dt =100 A/μs; VDS (peak) < V(BR)DSS, VDD = 640 V. 3. VDS ≤ 640 V. Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 2.08 °C/W Rthj-pcb (1) Thermal resistance junction-pcb 50 °C/W Value Unit 1. When mounted on FR-4 board of 1 inch², 2 oz Cu. Table 3. Avalanche characteristics Symbol DS11344 - Rev 4 Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by TJ max) 1.2 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR, VDD = 50 V) 165 mJ page 2/18 STD5N80K5 Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified Table 4. On/off-state Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage Min. VGS = 0 V, ID = 1 mA Typ. 800 Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0 V, VGS = ±20 V VGS(th) Gate threshold voltage VDD = VGS, ID = 100 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 2 A VGS = 0 V, VDS = 800 V, TC = 125 Unit V VGS = 0 V, VDS = 800 V IDSS Max. 1 °C(1) 50 µA ±10 µA 4 5 V 1.50 1.75 Ω Min. Typ. Max. Unit - 177 - pF - 15 - pF - 0.3 - pF - 33 - nC - 12 - nC - 16 - nC 3 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr) (1) Equivalent capacitance time related Co(er) (2) Equivalent capacitance energy related Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V VDS = 0 to 640 V, VGS = 0 V Rg Intrinsic gate resistance Qg Total gate charge VGS = 0 to 10 V - 5 - nC Qgs Gate-source charge - 1.7 - nC Qgd Gate-drain charge (see Figure 14. Test circuit for gate charge behavior) - 2.9 - nC VDD = 640 V, ID = 4 A, 1. Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. 2. Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS11344 - Rev 4 Parameter Test conditions Min. Typ. Max. Unit Turn-on delay time VDD = 400 V, ID = 2 A, - 12.7 - ns Rise time RG = 4.7 Ω, VGS = 10 V - 11.7 - ns Turn-off delay time (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) - 23 - ns - 14.8 - ns Fall time page 3/18 STD5N80K5 Electrical characteristics Table 7. Source-drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 4 A ISDM (1) Source-drain current (pulsed) - 16 A VSD (2) Forward on voltage - 1.5 V trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr ISD = 4 A, VGS = 0 V - 265 ns (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 1.59 μC - 12 A ISD = 4 A, di/dt = 100 A/μs, VDD = 60 V, - 386 ns - 2.18 μC - 11.3 A Min. Typ. Max. Unit 30 - - V ISD = 4 A, di/dt = 100 A/μs, VDD = 60 V Reverse recovery time TJ = 150 °C Qrr Reverse recovery charge IRRM Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 μs, duty cycle 1.5%. Table 8. Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS = ±1 mA, ID = 0 A The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DS11344 - Rev 4 page 4/18 STD5N80K5 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Thermal impedance Figure 1. Safe operating area GIPG270420161532SOA ID (A) Operation in this area is limited by R DS(on) 10 1 t p =10 µs t p =100 µs 10 0 t p =1 ms t p =10 ms 10 -1 T j ≤150 °C T c = 25°C single pulse 10 -2 10 -1 10 0 10 1 V DS (V) 10 2 Figure 3. Output characteristicsV GS =7, 8, 9, 10 V ID (A) GIPG210420161528OCH V GS =11 V 6 V GS =10 V 5 6 V DS =20 V 3 V GS =8 V 2 2 V GS =7 V 1 1 V GS =6 V 0 0 4 8 12 16 V DS (V) Figure 5. Gate charge vs gate-source voltage V GS (V) 600 1.8 500 1.7 400 1.6 300 1.5 200 1.4 100 1.3 0 Q g (nC) 1.2 0 V DD = 640 V I D =4 A 8 6 Q gd 4 Q gs 1 2 3 4 5 5 6 7 8 9 10 11 V GS (V) Figure 6. Static drain-source on-resistance R DS(on) (Ω) (V) 10 0 4 GIPG210420161527QVG V DS V DS 12 DS11344 - Rev 4 GIPG210420161528TCH 4 3 0 0 ID (A) 5 V GS =9 V 4 2 Figure 4. Transfer characteristics V GS =8 V GIPG210420161528RID V GS =10 V 1 2 3 4 I D (A) page 5/18 STD5N80K5 Electrical characteristics (curves) Figure 7. Capacitance variations C (pF) GIPG210420161526CVR Figure 8. Normalized gate threshold voltage vs temperature V GS(th) (norm.) 10 3 GIPG210420161529VTH 1.2 C ISS 10 2 I D = 100 µA 1.0 0.8 10 1 10 0 10 -1 C OSS C RSS f = 1 MHz 0.6 0.4 10 -1 10 0 10 1 10 2 V DS (V) Figure 9. Normalized on-resistance vs temperature R DS(on) (norm.) GIPG210420161531RON 2.6 0.2 -75 -25 2.2 75 125 T j (°C) Figure 10. Normalized V(BR)DSS vs temperature V (BR)DSS (norm.) GIPG210420161529BDV 1.08 V GS = 10 V 25 I D = 1 mA 1.04 1.8 1.00 1.4 0.96 1.0 0.92 0.6 0.2 -75 -25 25 75 125 T j (°C) Figure 11. Maximum avalanche energy vs starting TJ E AS (mJ) GIPG210420161532EAS Single pulse I D =1.2 A V DD =50 V 150 0.88 -75 V SD (V) 90 0.8 60 0.7 30 0.6 DS11344 - Rev 4 25 75 125 T J (°C) 75 125 T j (°C) GIPG210420161530SDF T j = -50 °C 1.0 0.9 -25 25 Figure 12. Source-drain diode forward characteristics 120 0 -75 -25 0.5 0 T j = 25 °C T j = 150 °C 1 2 3 4 I SD (A) page 6/18 STD5N80K5 Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD RL RL 2200 + μF 3.3 μF VDD VD IG= CONST VGS + pulse width RG VGS D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v10 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A VD 100 µH fast diode B B B 3.3 µF D G + Figure 16. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) toff td(off) tr tf VD 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS11344 - Rev 4 page 7/18 STD5N80K5 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DS11344 - Rev 4 page 8/18 STD5N80K5 DPAK (TO-252) type A package information 4.1 DPAK (TO-252) type A package information Figure 19. DPAK (TO-252) type A package outline 0068772_A_26 DS11344 - Rev 4 page 9/18 STD5N80K5 DPAK (TO-252) type A package information Table 9. DPAK (TO-252) type A mechanical data Dim. mm Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 4.60 4.70 4.80 e 2.159 2.286 2.413 e1 4.445 4.572 4.699 H 9.35 10.10 L 1.00 1.50 (L1) 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 DS11344 - Rev 4 Typ. 5.10 5.25 6.60 1.00 0.20 0° 8° page 10/18 STD5N80K5 DPAK (TO-252) type C package information 4.2 DPAK (TO-252) type C package information Figure 20. DPAK (TO-252) type C package outline 0068772_C_26 DS11344 - Rev 4 page 11/18 STD5N80K5 DPAK (TO-252) type C package information Table 10. DPAK (TO-252) type C mechanical data Dim. mm Min. Typ. Max. A 2.20 2.30 2.38 A1 0.90 1.01 1.10 A2 0.00 0.10 b 0.72 0.85 b4 5.13 c 0.47 0.60 c2 0.47 0.60 D 6.00 D1 5.25 E 6.50 E1 4.70 e 5.46 6.10 6.20 6.60 6.70 2.186 2.286 2.386 H 9.80 10.10 10.40 L 1.40 1.50 1.70 L1 L2 2.90 REF 0.90 L3 L4 1.25 0.51 BSC 0.60 L6 DS11344 - Rev 4 5.33 0.80 1.00 1.80 BSC θ1 5° 7° 9° θ2 5° 7° 9° V2 0° 8° page 12/18 STD5N80K5 DPAK (TO-252) type C package information Figure 21. DPAK (TO-252) recommended footprint (dimensions are in mm) FP_0068772_26 DS11344 - Rev 4 page 13/18 STD5N80K5 DPAK (TO-252) packing information 4.3 DPAK (TO-252) packing information Figure 22. DPAK (TO-252) tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 K0 For machine ref. only including draft and radii concentric around B0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 DS11344 - Rev 4 page 14/18 STD5N80K5 DPAK (TO-252) packing information Figure 23. DPAK (TO-252) reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 11. DPAK (TO-252) tape and reel mechanical data Tape Dim. mm mm Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 DS11344 - Rev 4 Reel Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 18.4 22.4 page 15/18 STD5N80K5 Revision history Table 12. Document revision history Date 08-Jan-2016 Revision Changes 1 First release. Modified: title Modified: Table 1. Absolute maximum ratings, Table 2. Thermal data, Table 4. On/off-state, Table 5. Dynamic, Table 6. Switching times and Table 7. Source-drain diode. 09-May-2016 2 Added: Section 2.1 Electrical characteristics (curves). Modified: Section 3 Test circuits. Minor text changes DS11344 - Rev 4 03-Apr-2019 3 05-Jul-2019 4 Updated Section 4 Package information. Minor text changes. Updated Section 4 Package information. Minor text changes. page 16/18 STD5N80K5 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 DPAK (TO-252) type A package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 DPAK (TO-252) type C package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 DS11344 - Rev 4 page 17/18 STD5N80K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2019 STMicroelectronics – All rights reserved DS11344 - Rev 4 page 18/18