STD7N65M2

STD7N65M2 N-channel 650 V, 0.98 Ω typ., 5 A MDmesh™ M2 Power MOSFET in a DPAK package Datasheet - production data Features TAB Order code VDS RDS(on) max ID STD7N65M2 650 V 1.15 Ω 5A • Extremely low gate charge 3 1 • Excellent output capacitance (Coss) profile • 100% avalanche tested DPAK • Zener-protected Applications Figure 1. Internal schematic diagram • Switching applications Description D(2, TAB) This device is an N-channel Power MOSFET developed using the MDmesh™ M2 technology. Thanks to the strip layout associated to an improved vertical structure, the device exhibits both low on-resistance and optimized switching characteristics. It is therefore suitable for the most demanding high efficiency converters. G(1) S(3) AM15572v1 Table 1. Device summary Order code Marking Package Packaging STD7N65M2 7N65M2 DPAK Tape and reel May 2015 This is information on a product in full production. DocID026787 Rev 2 1/17 www.st.com Contents STD7N65M2 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Test circuits .............................................. 8 4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 DPAK (TO-252) type A package information . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 DPAK (TO-252) type C package information . . . . . . . . . . . . . . . . . . . . . . .11 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/17 DocID026787 Rev 2 STD7N65M2 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ± 25 V ID Drain current (continuous) at TC = 25 °C 5 A ID Drain current (continuous) at TC = 100 °C 3.2 A IDM(1) Drain current (pulsed) 20 A PTOT W Total dissipation at TC = 25 °C 60 dv/dt (2) Peak diode recovery voltage slope 15 dv/dt (3) MOSFET dv/dt ruggedness 50 Tstg Tj V/ns Storage temperature - 55 to 150 °C Value Unit Operating junction temperature 1. Pulse width limited by safe operating area 2. ISD ≤ 5 A, di/dt ≤ 400 A/µs; VDS peak < V(BR)DSS, VDD=400 V 3. VDS ≤ 520 V Table 3. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case max 2.08 °C/W Rthj-pcb Thermal resistance junction-pcb max 50(1) °C/W 1. When mounted on 1 inch² FR-4, 2 Oz copper board. Table 4. Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax ) 1 A EAS Single pulse avalanche energy (starting Tj=25°C, ID= IAR; VDD=50 V) 103 mJ DocID026787 Rev 2 3/17 17 Electrical characteristics 2 STD7N65M2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 5. On /off states Symbol V(BR)DSS Parameter Drain-source breakdown voltage IDSS Zero gate voltage drain current IGSS Gate-body leakage current Test conditions VGS = 0, ID = 1 mA Min. Typ. Max. Unit 650 V VGS = 0, VDS = 650 V 1 µA VGS = 0, VDS = 650 V, TC=125 °C 100 µA VDS = 0, VGS = ± 25 V ±10 µA 3 4 V 0.98 1.15 Ω Min. Typ. Max. Unit - 270 - pF - 14.5 - pF - 0.8 - pF VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance 2 VGS = 10 V, ID = 2.5 A Table 6. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 520 V, VGS = 0 - 108 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 7 - Ω Qg Total gate charge - 9 - nC Qgs Gate-source charge - 2.3 - nC Qgd Gate-drain charge VDD = 520 V, ID = 5 A, VGS = 10 V (see Figure 15) - 4.3 - nC VDS = 100 V, f = 1 MHz, VGS = 0 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS Table 7. Switching times Symbol td(on) tr td(off) tf 4/17 Parameter Test conditions Turn-on delay time Rise time Turn-off delay time VDD = 325 V, ID = 2.5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 14 and 19) Fall time DocID026787 Rev 2 Min. Typ. Max. Unit - 8 - ns - 20 - ns - 30 - ns - 20 - ns STD7N65M2 Electrical characteristics Table 8. Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 5 A ISDM (1) Source-drain current (pulsed) - 20 A VSD (2) Forward on voltage - 1.6 V ISD trr ISD = 5 A, VGS = 0 Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 5 A, di/dt = 100 A/µs VDD = 60 V (see Figure 19) ISD = 5 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C (see Figure 19) - 275 ns - 1.62 µC - 11.8 A - 430 ns - 2.54 µC - 11.9 A 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID026787 Rev 2 5/17 17 Electrical characteristics 2.1 STD7N65M2 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance GIPG060820141409FSR ID (A) 10 ) on S( O p Li e r a m ite tion d by i n t m his ax a R D rea is 10μs 1 100μs 1ms 10ms 0.1 Tj=150°C Tc=25°C Single pulse 0.01 0.1 1 10 100 VDS(V) Figure 4. Output characteristics Figure 5. Transfer characteristics GIPG060820141159FSR ID (A) VGS=7, 8, 9, 10V GIPG060820141210FSR ID (A) 8 VDS=20V 8 6V 6 6 4 4 5V 2 2 4V 0 0 10 5 20 15 Figure 6. Gate charge vs gate-source voltage GIPG060820141216FSR VDS VGS (V) RDS(on) (Ω) 600 1.04 10 500 1.02 8 400 1.0 6 300 0.98 4 200 0.96 2 100 0.94 VDS VDD=520V ID=5A 0 0 2 4 6 8 10 0 Qg(nC) 2 6 4 8 VGS(V) Figure 7. Static drain-source on-resistance (V) 12 6/17 0 0 VDS(V) GIPG060820141221FSR VGS=10V 0.92 DocID026787 Rev 2 0 1 2 3 4 5 ID(A) STD7N65M2 Electrical characteristics Figure 8. Capacitance variations Figure 9. Output capacitance stored energy GIPG060820141238FSR C (pF) 1000 GIPG060820141302FSR Eoss (μJ) 2.4 Ciss 100 1.8 10 Coss 1.2 1 Crss 0.6 0.1 0.1 1 100 10 0 0 VDS(V) Figure 10. Normalized gate threshold voltage vs temperature AM18065v1 VGS(th) (norm) 100 200 300 AM18066v1 RDS(on) ID=2.5A VGS=10V ID=250μA 1.1 2.2 1.0 1.8 0.9 1.4 0.8 1.0 0.7 0.6 25 0 25 75 125 TJ(°C) Figure 12. Source-drain diode forward characteristics GIPG060820141313FSR VSD (V) VDS(V) Figure 11. Normalized on-resistance vs temperature (norm) 0.6 -75 400 500 600 0.2 -75 -25 0 25 75 125 TJ(°C) Figure 13. Normalized V(BR)DSS vs temperature AM18067v1 V(BR)DSS (norm) TJ=-50°C 1.1 ID=1mA 1.08 1 1.04 0.9 TJ=25°C 1.00 0.8 0.96 0.7 0.6 0.5 0 0.92 TJ=150°C 1 2 3 4 5 ISD(A) 0.88 -75 DocID026787 Rev 2 -25 0 25 75 125 TJ(°C) 7/17 17 Test circuits 3 STD7N65M2 Test circuits Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF IG=CONST VDD VGS 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 Figure 16. Test circuit for inductive load switching and diode recovery times A A AM01469v1 Figure 17. Unclamped inductive load test circuit L A D G D.U.T. FAST DIODE B B VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform ton 9%5'66 tdon 9' toff tr tdoff tf 90% 90% ,'0 10% ,' 9'' 10% 0 9'' VDS 90% VGS $0Y 8/17 0 DocID026787 Rev 2 10% AM01473v1 STD7N65M2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 DPAK (TO-252) type A package information Figure 20. DPAK (TO-252) type A package outline B$B DocID026787 Rev 2 9/17 17 Package information STD7N65M2 Table 9. DPAK (TO-252) type A package mechanical data mm Dim. Min. Typ. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 4.60 4.70 4.80 e 2.16 2.28 2.40 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 (L1) 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 5.10 V2 5.25 6.60 1.00 R 10/17 Max. 0.20 0° 8° DocID026787 Rev 2 STD7N65M2 4.2 Package information DPAK (TO-252) type C package information Figure 21. DPAK (TO-252) type C package outline BBW\SHB& DocID026787 Rev 2 11/17 17 Package information STD7N65M2 Table 10. DPAK (TO-252) type C package mechanical data mm Dim. Min. Typ. Max. A 2.20 2.30 2.38 A1 0.90 1.01 1.10 A2 0.00 0.10 b 0.72 0.85 b4 5.13 c 0.47 0.60 c2 0.47 0.60 D 6.00 D1 5.25 E 5.33 6.10 6.20 6.50 6.60 6.70 e 2.186 2.286 2.386 E1 4.70 H 9.80 10.10 10.40 L 1.40 1.50 1.70 L1 L2 2.90 REF 0.90 1.25 L3 L4 0.51 BSC 0.60 0.80 L6 12/17 5.46 1.00 1.80 BSC Θ1 5° 7° 9° Θ2 5° 7° 9° V2 0° 8° DocID026787 Rev 2 STD7N65M2 Package information Figure 22. DPAK footprint (a) )3B4 a. All dimensions are in millimeters DocID026787 Rev 2 13/17 17 Packaging mechanical data 5 STD7N65M2 Packaging mechanical data Figure 23. Tape for DPAK (TO-252) 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 K0 For machine ref. only including draft and radii concentric around B0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 14/17 DocID026787 Rev 2 STD7N65M2 Packaging mechanical data Figure 24. Reel for DPAK (TO-252) T REEL DIMENSIONS 40mm min. Access hole At slot location B D C N A Full radius G measured at hub Tape slot in core for tape start 25 mm min. width AM08851v2 Table 11. DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 DocID026787 Rev 2 18.4 22.4 15/17 17 Revision history 6 STD7N65M2 Revision history Table 12. Document revision history 16/17 Date Revision Changes 07-Aug-2014 1 First release. 06-May-2015 2 Document status promoted from preliminary to production data. Updated Section 4: Package information. DocID026787 Rev 2 STD7N65M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID026787 Rev 2 17/17 17