STD7N65M6

STD7N65M6 Datasheet N-channel 650 V, 0.91 Ω typ., 5 A, MDmesh™ M6 Power MOSFET in a DPAK package Features TAB 2 3 1 DPAK D(2, TAB) Order code VDS RDS(on) max. ID STD7N65M6 650 V 0.99 Ω 5A • • Reduced switching losses Lower RDS(on) per area vs previous generation • • • Low gate input resistance 100% avalanche tested Zener-protected Applications G(1) • S(3) AM01475V1 Switching applications Description The new MDmesh™ M6 technology incorporates the most recent advancements to the well-known and consolidated MDmesh family of SJ MOSFETs. STMicroelectronics builds on the previous generation of MDmesh devices through its new M6 technology, which combines excellent RDS(on) per area improvement with one of the most effective switching behaviors available, as well as a user-friendly experience for maximum end-application efficiency. Product status link STD7N65M6 Product summary Order code STD7N65M6 Marking 7N65M6 Package DPAK Packing Tape and reel DS11776 - Rev 2 - October 2018 For further information contact your local STMicroelectronics sales office. www.st.com STD7N65M6 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ±25 V ID Drain current (continuous) at TC = 25 °C 5 A ID Drain current (continuous) at TC = 100 °C 3.2 A IDM(1) Drain current (pulsed) 20 A PTOT Total power dissipation at TC = 25 °C 60 W dv/dt(2) Peak diode recovery voltage slope 5 dv/dt(3) MOSFET dv/dt ruggedness 50 TJ Operating junction temperature range Tstg Storage temperature range V/ns -55 to 150 °C Value Unit 1. Pulse width limited by safe operating area. 2. ISD ≤ 5 A, di/dt ≤ 400 A/μs, VDS peak < V(BR)DSS, VDD = 400 V 3. VDS ≤ 520 V Table 2. Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter Thermal resistance junction-case 2.08 Thermal resistance junction-pcb 50 °C/W 1. When mounted on FR-4 board of inch², 2oz Cu. Table 3. Avalanche characteristics Symbol DS11776 - Rev 2 Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 1.5 A Eas Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 95 mJ page 2/18 STD7N65M6 Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified Table 4. On/off state Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS= 0, ID = 1 mA Min. Typ. 650 Zero gate voltage drain current 1 µA 100 µA ±5 µA 3 3.75 V 0.91 0.99 Ω Min. Typ. Max. Unit - 220 - pF - 25 - pF - 1.1 - pF VGS = 0 V, VDS = 650 V, TC = 125 °C(1) IGSS Gate body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 2.5 A Unit V VGS = 0 V, VDS = 650 V IDSS Max. 2.25 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 520 V, VGS = 0 V - 45 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 6.3 - Ω Qg Total gate charge VDD = 520 V, ID = 5 A, - 6.9 - nC Qgs Gate-source charge VGS = 0 to 10 V - 1.3 - nC Qgd Gate-drain charge (see Figure 14. Test circuit for gate charge behavior) - 3.1 - nC VDS = 100 V, f = 1 MHz, VGS = 0 V 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS11776 - Rev 2 Parameter Test conditions Min. Typ. Max. Unit Turn-on delay time VDD = 325 V, ID = 2.5 A, - 6.5 - ns Rise time RG = 4.7 Ω, VGS = 10 V - 4.5 - ns Turn-off delay time (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) - 21.4 - ns - 12.4 - ns Fall time page 3/18 STD7N65M6 Electrical characteristics Table 7. Source-drain diode Symbol ISD ISDM(1) (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 5 A Source-drain current (pulsed) - 20 A 1.6 V Forward on voltage ISD = 5 A, VGS = 0 V - trr Reverse recovery time ISD = 5 A, di/dt = 100 A/µs, - 171 ns Qrr Reverse recovery charge VDD = 60 V - 1 µC Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 11.8 A trr Reverse recovery time ISD = 5 A, di/dt = 100 A/µs, - 234 ns Qrr Reverse recovery charge VDD = 60 V, Tj = 150 °C - 1.2 µC IRRM Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 10.8 A VSD IRRM 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%. DS11776 - Rev 2 page 4/18 STD7N65M6 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Thermal impedance Figure 1. Safe operating area ID (A) GIPG280720161455SOA Operation in this area 10 1 is limited by R DS(on) tp =10 µs n) tp =100 µs 10 0 tp =1 ms tp =10 ms Single pulse, Tc = 25 °C TJ ≤ 150 °C, VGS= 10 V 10 -1 10 -2 10 -1 10 0 10 1 V DS (V) 10 2 Figure 3. Output characteristics ID (A) Figure 4. Transfer characteristics ID (A) GIPG290720160921OCH VGS = 6 V 8 GIPG290720161033TCH VDS =14 V 8 6 6 VGS=5 V 4 4 2 2 VGS = 4 V 0 0 2 4 6 8 10 12 V DS (V) Figure 5. Gate charge vs gate-source voltage VGS (V) 2 4 6 GIPG020820160837QVG VDS (V) 500 0.95 400 0.93 6 300 0.91 4 200 0.89 2 100 0.87 0 Qg (nC) 0.85 0 10 VDD = 520 V ID = 5 A 8 0 0 1 2 3 4 5 6 7 8 V GS (V) GIPG290720161116RID 600 VDS 8 Figure 6. Static drain-source on-resistance Ω 0.97 12 DS11776 - Rev 2 0 0 VGS=10 V 1 2 3 4 5 IC (A) page 5/18 STD7N65M6 Electrical characteristics (curves) Figure 8. Normalized gate threshold voltage vs temperature Figure 7. Capacitance variations C (pF) GIPG290720161128CVR 10 3 V GS(th) (norm.) GIPG290720161143VTH ID=250 µA 1.1 C ISS 1 10 2 0.9 C OSS 10 1 f = 1 MHz 0.8 C RSS 10 0 0.7 10 -1 10 -1 10 0 10 1 V DS (V) 10 2 Figure 9. Normalized on-resistance vs temperature R DS(on) (norm.) GIPG290720161206RON V GS =10 V 2.2 0.6 -75 1 1 0.96 0.6 0.92 75 125 0.88 -75 ° Figure 11. Output capacitance stored energy GIPG290720161227EOS E (μJ) 2 1 1.6 0.9 1.2 0.8 0.8 0.7 0.4 0.6 DS11776 - Rev 2 200 300 400 500 600 V DS (V) ID= 1 mA -25 25 75 V SD (V) 1.1 100 TJ (°C) ° 125 Figure 12. Source-drain diode forward characteristics 2.4 0 0 125 GIPG290720161215BDV 1.08 1.4 25 75 V (BR)DSS (norm.) 1.04 -25 25 Figure 10. Normalized V(BR)DSS vs temperature 1.8 0.2 -75 -25 0.5 0 GIPG290720161328SDF Tj = 50 °C Tj = 25 °C Tj = 150 °C 1 2 3 4 5 I SD (A) page 6/18 STD7N65M6 Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD RL RL 2200 + μF 3.3 μF VDD VD RG VGS IG= CONST VGS + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v10 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A VD 100 µH fast diode B B B 3.3 µF D G + Figure 16. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) toff td(off) tr tf VD 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS11776 - Rev 2 page 7/18 STD7N65M6 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS11776 - Rev 2 page 8/18 STD7N65M6 DPAK (TO-252) type A package information 4.1 DPAK (TO-252) type A package information Figure 19. DPAK (TO-252) type A package outline 0068772_A_25 DS11776 - Rev 2 page 9/18 STD7N65M6 DPAK (TO-252) type A package information Table 8. DPAK (TO-252) type A mechanical data Dim. mm Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 4.60 4.70 4.80 e 2.159 2.286 2.413 e1 4.445 4.572 4.699 H 9.35 10.10 L 1.00 1.50 (L1) 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 DS11776 - Rev 2 Typ. 5.10 5.25 6.60 1.00 0.20 0° 8° page 10/18 STD7N65M6 DPAK (TO-252) type C package information 4.2 DPAK (TO-252) type C package information Figure 20. DPAK (TO-252) type C package outline 0068772_C_25 DS11776 - Rev 2 page 11/18 STD7N65M6 DPAK (TO-252) type C package information Table 9. DPAK (TO-252) type C mechanical data Dim. mm Min. Typ. Max. A 2.20 2.30 2.38 A1 0.90 1.01 1.10 A2 0.00 0.10 b 0.72 0.85 b4 5.13 c 0.47 0.60 c2 0.47 0.60 D 6.00 D1 5.25 E 6.50 E1 4.70 e 5.46 6.10 6.20 6.60 6.70 2.186 2.286 2.386 H 9.80 10.10 10.40 L 1.40 1.50 1.70 L1 L2 2.90 REF 0.90 L3 L4 1.25 0.51 BSC 0.60 L6 DS11776 - Rev 2 5.33 0.80 1.00 1.80 BSC θ1 5° 7° 9° θ2 5° 7° 9° V2 0° 8° page 12/18 STD7N65M6 DPAK (TO-252) type C package information Figure 21. DPAK (TO-252) recommended footprint (dimensions are in mm) FP_0068772_25_C DS11776 - Rev 2 page 13/18 STD7N65M6 DPAK (TO-252) packing information 4.3 DPAK (TO-252) packing information Figure 22. DPAK (TO-252) tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 K0 For machine ref. only including draft and radii concentric around B0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 DS11776 - Rev 2 page 14/18 STD7N65M6 DPAK (TO-252) packing information Figure 23. DPAK (TO-252) reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 10. DPAK (TO-252) tape and reel mechanical data Tape Dim. mm mm Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 DS11776 - Rev 2 Reel Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 18.4 22.4 page 15/18 STD7N65M6 Revision history Table 11. Document revision history Date Revision 03-Aug-2016 1 Changes Initial release. Updated Figure 14. Test circuit for gate charge behavior. 15-Oct-2018 2 Updated Section 4 Package information. Minor text changes DS11776 - Rev 2 page 16/18 STD7N65M6 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 DPAK (TO-252) type A package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 DPAK (TO-252) type C package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 DS11776 - Rev 2 page 17/18 STD7N65M6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS11776 - Rev 2 page 18/18