STD7N90K5

STD7N90K5 Datasheet N-channel 900 V, 0.72 Ω typ., 7 A MDmesh™ K5 Power MOSFET in a DPAK package Features TAB 2 3 1 DPAK D(2, TAB) Order code VDS RDS(on ) max. ID STD7N90K5 900 V 0.81 Ω 7A • Industry’s lowest RDS(on) x area • • • • Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Applications G(1) • Switching applications Description S(3) AM01475V1 This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Product status STD7N90K5 Product summary Order code STD7N90K5 Marking 7N90K5 Package DPAK Packing Tape and reel DS11870 - Rev 2 - February 2018 For further information contact your local STMicroelectronics sales office. www.st.com STD7N90K5 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter VGS Gate-source voltage Value Unit ± 30 V ID Drain current (continuous) at TC = 25 °C 7 A ID Drain current (continuous) at TC = 100 °C 4.4 A ID (1) Drain current (pulsed) 28 A PTOT Total dissipation at TC = 25 °C 90 W dv/dt (2) Peak diode recovery voltage slope 4.5 dv/dt (3) MOSFET dv/dt ruggedness 50 Tj Operating junction temperature range Tstg Storage temperature range V/ns - 55 to 150 °C 1. Pulse width limited by safe operating area 2. ISD ≤ 7 A, di/dt ≤ 100 A/μs; VDS peak < V(BR)DSS, VDD = 450 V 3. VDS ≤ 720 V Table 2. Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter Value Unit Thermal resistance junction-case 1.38 °C/W Thermal resistance junction-pcb 50 °C/W 1. When mounted on 1 inch² FR-4 board, 2 oz Cu. Table 3. Avalanche characteristics Symbol DS11870 - Rev 2 Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 2.4 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 230 mJ page 2/16 STD7N90K5 Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified Table 4. On/off-state Symbol Parameter Test conditions Min. V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA 900 Typ. IDSS 1 µA 50 µA ±10 µA 4 5 V 0.72 0.81 Ω Min. Typ. Max. Unit - 425 - pF - 41 - pF - 1.2 - pF - 64 - pF VGS = 0 V, VDS = 900 V TC = 125 °C (1) IGSS Gate body leakage current VDS = 0 V, VGS = ±20 V VGS(th) Gate threshold voltage VDD = VGS, ID = 100 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 3.5 A Unit V VGS = 0 V, VDS = 900 V Zero gate voltage drain current Max. 3 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr) (1) Equivalent capacitance time related Co(er) (2) Equivalent capacitance energy related Rg Intrinsic gate resistance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V VGS = 0 V, VDS = 0 to 720 V 24 f = 1 MHz , ID = 0 A VDD = 720 V, ID = 7 A, VGS = 0 to 10 V; (see Figure 14. Test circuit for gate charge behavior) pF - 6.7 - Ω - 12 - nC - 3.5 - nC - 6.5 - nC 1. Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. 2. Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS11870 - Rev 2 Parameter Test conditions Turn-on delay time Rise time Turn-off delay time Fall time Min. Typ. Max. Unit VDD= 450 V, ID = 3.5 A, RG = 4.7 Ω, - 13.2 - ns VGS = 10 V; (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) - 14.2 - ns - 31.6 - ns - 14.7 - ns page 3/16 STD7N90K5 Electrical characteristics Table 7. Source-drain diode Symbol ISD ISDM (1) (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 7 A Source-drain current (pulsed) - 28 A 1.5 V Forward on voltage ISD = 7 A, VGS = 0 V - trr Reverse recovery time ISD = 7 A, di/dt = 100 A/µs,VDD = 60 V - 352 ns Qrr Reverse recovery charge - 3.63 µC IRRM Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 20.6 A - 525 ns - 4.94 µC - 18.8 A VSD trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 7 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C (see Figure 15. Test circuit for inductive load switching and diode recovery times) 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 8. Gate-source Zener diode Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)GSO Gate-source breakdown voltage IGS= ± 1mA, ID= 0 A ±30 - - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DS11870 - Rev 2 page 4/16 STD7N90K5 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area ID (A) 10 1 Figure 2. Thermal impedance GADG121020161023SOA Operation in this area is limited by R DS(on) GC20460 K tp= 10 µs tp= 100µs 10 0 100 tp= 1 ms tp= 10 ms 10-1 10 -1 single pulse T j ≤150 °C T c = 25 °C 10 -2 10 -1 10 0 10 1 10 2 10 3 V DS (V) 10-2 10-5 Figure 3. Output characteristics ID (A) 10-4 10-3 10-2 10-1 tp (s) Figure 4. Transfer characteristics ID (A) GIPG051020161339OCH GIPG051020161340TCH V DS =20 V VGS = 11 V 15 15 VGS = 10 V 10 10 VGS = 9 V VGS = 8 V 5 5 VGS = 7 V VGS = 6 V 0 0 4 8 12 16 V DS (V) Figure 5. Gate charge vs gate-source voltage VGS (V) GIPG051020161340QVG VDS (V) VDS 14 500 8 400 4 300 Qgd Qgs DS11870 - Rev 2 8 9 10 V GS (V) Figure 6. Static drain-source on-resistance GIPG051020161341RID R DS(on) [Ω] V GS =10 V 0.8 0.7 200 2 0 0 7 600 10 6 6 700 VDD = 720 V ID = 7 A 12 0 5 100 2 4 6 8 10 12 14 0 Qg (nC) 0.6 0 2 4 6 I D (A) page 5/16 STD7N90K5 Electrical characteristics (curves) Figure 7. Capacitance variations C (pF) Figure 8. Normalized VGS(th) vs temperature GIPG051020161342CVR V GS(th) (norm.) GIPG051020161343VTH I D = 100 µA 1.2 1000 100 C ISS 1 f =1 MHz 0.8 C OSS 0.6 10 C RSS 1 0.1 1 10 100 0.4 V DS (V) Figure 9. Normalized on-resistance vs temperature R DS(on) (norm.) GIPG051020161344RON 2.6 V GS = 10 V 0.2 -50 V (BR)DSS (norm.) 1.8 1.04 1.4 1.00 1 0.96 0.6 0.92 50 100 T j (°C) Figure 11. Maximum avalanche energy vs starting TJ EAS (mJ) GADG061020160850EAS 100 T j (°C) GIPG051020161345BDV 1.12 1.08 0 50 Figure 10. Normalized V(BR)DSS vs temperature 2.2 0.2 -50 0 I D = 1 mA 0.88 -50 0 50 100 T j (°C) Figure 12. Source-drain diode forward characteristics V SD (V) GADG071020160858SDF 1 Single pulse ID =2.4 A,VDD =50 V T j = -50 °C 0.9 200 0.8 0.7 100 T j = 25 °C T j = 150 °C 0.6 0 -50 DS11870 - Rev 2 0 50 100 TJ (°C) 0.5 1 2 3 4 5 6 I SD (A) page 6/16 STD7N90K5 Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD RL RL 2200 + μF 3.3 μF VDD VD + pulse width RG VGS IG= CONST VGS 2.7 kΩ 2200 μF D.U.T. D.U.T. 100 Ω VG 47 kΩ pulse width 1 kΩ AM01469v10 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times Figure 16. Unclamped inductive load test circuit L D G A D.U.T. S 25 Ω A A 100 µH fast diode B B B VD 3.3 µF D G + RG 1000 + µF 2200 + µF 3.3 µF VDD ID VDD D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform V(BR)DSS VD ton td(on) IDM toff td(off) tr 90% 90% 10% ID VDD tf VDD 10% 0 VGS AM01472v1 0 VDS 90% 10% AM01473v1 DS11870 - Rev 2 page 7/16 STD7N90K5 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS11870 - Rev 2 page 8/16 STD7N90K5 DPAK (TO-252) type A2 package information 4.1 DPAK (TO-252) type A2 package information Figure 19. DPAK (TO-252) type A2 package outline 0068772_type-A2_rev24 DS11870 - Rev 2 page 9/16 STD7N90K5 DPAK (TO-252) type A2 package information Table 9. DPAK (TO-252) type A2 mechanical data Dim. mm Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 5.10 5.20 5.30 e 2.16 2.28 2.40 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 L1 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 DS11870 - Rev 2 Typ. 5.10 5.25 6.60 1.00 0.20 0° 8° page 10/16 STD7N90K5 DPAK (TO-252) type A2 package information Figure 20. DPAK (TO-252) recommended footprint (dimensions are in mm) FP_0068772_24 DS11870 - Rev 2 page 11/16 STD7N90K5 DPAK (TO-252) packing information 4.2 DPAK (TO-252) packing information Figure 21. DPAK (TO-252) tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 K0 For machine ref. only including draft and radii concentric around B0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 DS11870 - Rev 2 page 12/16 STD7N90K5 DPAK (TO-252) packing information Figure 22. DPAK (TO-252) reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 10. DPAK (TO-252) tape and reel mechanical data Tape Dim. mm mm Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 DS11870 - Rev 2 Reel Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 18.4 22.4 page 13/16 STD7N90K5 Revision history Table 11. Document revision history Date Revision 14-Oct-2016 1 Changes First release. Removed maturity status indication from cover page. 20-Feb-2018 2 The document status is production data. Updated Table 5. Dynamic and Figure 5. Gate charge vs gate-source voltage. Minor text changes. DS11870 - Rev 2 page 14/16 STD7N90K5 Contents Contents 1 Electrical ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 DPAK (TO-252) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 DPAK (TO-252) packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 DS11870 - Rev 2 page 15/16 STD7N90K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS11870 - Rev 2 page 16/16