STD7NM64N

STD7NM64N N-channel 640 V, 5 A, 0.88 Ω typ., MDmesh™ II Power MOSFET in a DPAK package Datasheet - production data Features TAB Order code VDS RDS(on) max. ID STD7NM64N 640 V 1.05 Ω 5A • 100% avalanche tested 3 • Low input capacitance and gate charge 1 • Low gate input resistance DPAK Applications • Switching applications Figure 1. Internal schematic diagram Description This device is an N-channel Power MOSFET developed using the second generation of MDmesh™ technology. This revolutionary Power MOSFET associates a vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters. '7$% * 6 $0Y Table 1. Device summary Order code Marking Packages Packaging STD7NM64N 7NM64N DPAK Tape and reel August 2013 This is information on a product in full production. DocID025081 Rev 1 1/16 www.st.com Contents STD7NM64N Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2/16 .............................................. 8 DocID025081 Rev 1 STD7NM64N 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 640 V VGS Gate-source voltage ± 25 V ID Drain current (continuous) at TC = 25 °C 5 A ID Drain current (continuous) at TC = 100 °C 3 A Drain current (pulsed) 20 A Total dissipation at TC = 25 °C 60 W Peak diode recovery voltage slope 15 V/ns MOSFET dv/dt ruggedness 50 V/ns - 55 to 150 °C 150 °C Value Unit IDM (1) PTOT dv/dt (2) dv/dt (3) Tstg Tj Storage temperature Max. operating junction temperature 1. Pulse width limited by safe operating area 2. ISD ≤ 5 A, di/dt ≤ 400 A/µs, VDS(peak) < V(BR)DSS 3. VDS ≤ 512 V Table 3. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case max 2.08 °C/W Rthj-pcb(1) Thermal resistance junction-pcb max 50 °C/W Value Unit 1. When mounted on 1 inch² FR-4, 2 Oz copper board Table 4. Thermal data Symbol Parameter IAR Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max) 2 A EAS Single pulse avalanche energy (starting Tj = 25°C, ID = IAR, VDD = 50 V) 119 mJ DocID025081 Rev 1 3/16 16 Electrical characteristics 2 STD7NM64N Electrical characteristics (TC = 25 °C unless otherwise specified). Table 5. On /off states Symbol V(BR)DSS Parameter Drain-source breakdown voltage (VGS = 0) IDSS Zero gate voltage drain current IGSS Gate-body leakage current (VDS = 0) Test conditions ID = 1 mA Min. Typ. Max. Unit 640 V VDS = 640 V 1 µA VDS = 640 V, TC=125 °C 100 µA VGS = ± 20 V ±100 nA 3 4 V 0.88 1.05 Ω Min. Typ. Max. Unit - 363 - pF - 24.6 - pF - 1.1 - pF VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance 2 VGS = 10 V, ID = 2.5 A Table 6. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 - 130 - pF RG Intrinsic gate resistance f = 1 MHz, ID=0 - 5.4 - Ω Qg Total gate charge - 14 - nC Qgs Gate-source charge - 2.7 - nC Qgd Gate-drain charge VDD = 480 V, ID = 5 A, VGS = 10 V (see Figure 14) - 7.7 - nC VDS = 50 V, f = 1 MHz, VGS = 0 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDS. 4/16 DocID025081 Rev 1 STD7NM64N Electrical characteristics Table 7. Switching times Symbol td(on) tr Parameter Test conditions Turn-on delay time VDD = 300 V, ID = 2.5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 13) Rise time td(off) tf Turn-off-delay time Fall time Min. Typ. Max Unit - 7 - ns - 10 - ns - 26 - ns - 12 - ns Min. Typ. Table 8. Source drain diode Symbol Parameter Test conditions Max. Unit Source-drain current - 5 A ISDM (1) Source-drain current (pulsed) - 20 A VSD (2) Forward on voltage - 1.3 V ISD trr ISD = 5 A, VGS = 0 Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 5 A, di/dt = 100 A/µs VDD = 60 V (see Figure 18) ISD = 5 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C (see Figure 18) - 213 ns - 1.5 μC - 14 A - 265 ns - 1.8 μC - 14 A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID025081 Rev 1 5/16 16 Electrical characteristics 2.1 STD7NM64N Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance AM15980v1 ID (A) Op Lim era ite tion d by in t m his ax a RD rea S( on is 10 ) 10µs 1 100µs 1ms 10ms 0.1 Tj=150°C Tc=25°C Single pulse 0.01 0.1 10 1 VDS(V) 100 Figure 4. Output characteristics Figure 5. Transfer characteristics AM06477v1 AM06478v1 10 ID (A) 9 VGS=10V 8 7 7 6 6 ID (A) 5 5 4 4 5V 3 3 2 2 1 1 0 0 20 10 30 AM06479v1 VGS (V) VDD=480V ID=5A 12 0 0 VDS(V) Figure 6. Gate charge vs gate-source voltage 10 VDS=20V 9 6V 8 VDS (V) 500 VDS 400 8 2 4 6 8 10 VGS(V) Figure 7. Static drain-source on-resistance AM15981v1 RDS(on) (Ω) VGS=10V 0.940 0.920 0.900 300 0.880 6 200 4 2 0 0 6/16 2 4 6 8 10 12 14 16 0.860 100 0.840 0 Qg(nC) 0.820 DocID025081 Rev 1 0 1 2 3 4 5 ID(A) STD7NM64N Electrical characteristics Figure 8. Capacitance variations Figure 9. Output capacitance stored energy AM06481v1 C (pF) AM06482v1 Eoss (µJ) 2.5 1000 Ciss 2.0 1.5 100 Coss 10 1.0 0.5 Crss 1 0.1 1 100 10 Figure 10. Normalized gate threshold voltage vs temperature AM06483v1 VGS(th) 0 0 VDS(V) (norm) 100 200 300 400 500 600 VDS(V) Figure 11. Normalized on-resistance vs temperature AM06484v1 RDS(on) (norm) 1.10 ID=2.5A 2.1 ID=250µA 1.9 1.00 1.7 1.5 1.3 0.90 1.1 0.9 0.80 0.7 0.70 -50 -25 0 25 50 75 100 TJ(°C) 0.5 -50 -25 0 25 50 75 100 TJ(°C) Figure 12. Normalized VDS vs temperature AM15982v1 VDS (norm) 1.10 ID=1mA 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 -50 -25 0 25 50 75 100 TJ(°C) DocID025081 Rev 1 7/16 16 Test circuits 3 STD7NM64N Test circuits Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF IG=CONST VDD VGS 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times A A AM01469v1 Figure 16. Unclamped inductive load test circuit L A D G D.U.T. FAST DIODE B B VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 8/16 0 DocID025081 Rev 1 10% AM01473v1 STD7NM64N 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID025081 Rev 1 9/16 16 Package mechanical data STD7NM64N Table 9. DPAK (TO-252) mechanical data mm Dim. Min. Typ. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 E 5.10 6.40 6.60 E1 4.70 e 2.28 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 (L1) 2.80 L2 0.80 L4 0.60 1.00 R V2 10/16 Max. 0.20 0° 8° DocID025081 Rev 1 STD7NM64N Package mechanical data Figure 19. DPAK (TO-252) drawing 0068772_K_type_A DocID025081 Rev 1 11/16 16 Package mechanical data STD7NM64N Figure 20. DPAK footprint (a) Footprint_REV_K a. All dimensions are in millimeters 12/16 DocID025081 Rev 1 STD7NM64N 5 Packaging mechanical data Packaging mechanical data Table 10. DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 DocID025081 Rev 1 18.4 22.4 13/16 16 Packaging mechanical data STD7NM64N Figure 21. Tape for DPAK (TO-252) 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 W K0 B0 For machine ref. only including draft and radii concentric around B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 Figure 22. Reel for DPAK (TO-252) T REEL DIMENSIONS 40mm min. Access hole At slot location B D C N A Full radius Tape slot in core for tape start 25 mm min. width G measured at hub AM08851v2 14/16 DocID025081 Rev 1 STD7NM64N 6 Revision history Revision history Table 11. Document revision history Date Revision 02-Aug-2013 1 Changes First release. DocID025081 Rev 1 15/16 16 STD7NM64N Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. ST PRODUCTS ARE NOT AUTHORIZED FOR USE IN WEAPONS. NOR ARE ST PRODUCTS DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B) AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2013 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 16/16 DocID025081 Rev 1