STD80N3LL

STD80N3LL N-channel 30 V, 4 mΩ typ., 80 A Power MOSFET in a DPAK package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STD80N3LL 30 V 5.2 mΩ 80 A 75 W     Figure 1: Internal schematic diagram Very low on-resistance Very low gate charge High avalanche ruggedness Low gate drive power loss Applications  Switching applications D(2, TAB) Description This device is an N-channel Power MOSFET with very low RDS(on) in all packages. G(1) S(3) AM01475v1_Tab Table 1: Device summary Order code Marking Package Packaging STD80N3LL 80N3LL DPAK Tape and reel December 2016 DocID029591 Rev 2 This is information on a product in full production. 1/15 www.st.com Contents STD80N3LL Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 5 3 Test circuits ..................................................................................... 7 4 Package information ....................................................................... 8 5 2/15 4.1 DPAK package information ............................................................... 9 4.2 DPAK (TO-252) packing information ............................................... 12 Revision history ............................................................................ 14 DocID029591 Rev 2 STD80N3LL 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 30 V VGS Gate-source voltage ±20 V ID(1) Drain current (continuous) at TC = 25 °C 80 A ID(1) Drain current (continuous) at TC = 100 °C 60 A Drain current (pulsed) 320 A Total dissipation at TC = 25 °C 75 W -55 to 175 °C IDM(1)(2) PTOT (1) Tj Operating junction temperature range Tstg Storage temperature range Notes: (1)This value is limited by package (2)Pulse width limited by safe operating area Table 3: Thermal data Symbol Rthj-pcb (1) Rthj-case Parameter Value Unit Thermal resistance junction-pcb max. 50 °C/W Thermal resistance junction-case max. 2 °C/W Notes: (1)When mounted on FR-4 board of 1 inch², 2oz Cu DocID029591 Rev 2 3/15 Electrical characteristics 2 STD80N3LL Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4: On/off states Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage ID = 1 mA, VGS = 0 V IDSS Zero gate voltage drain current VGS = 0 V VDS = 30 V IGSS Gate-body leakage current VGS = 20 V, VDS = 0 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 μA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 40 A VGS = 4.5 V, ID = 40 A Min. Typ. Max. 30 Unit V 1 µA 100 nA 2.5 V 4 5.2 mΩ 5.5 6.5 mΩ Min. Typ. Max. Unit - 1640 - - 207 - - 160 - - 18 - - 5.3 - - 8.8 - Min. Typ. Max. Unit - 6.4 - ns - 8 - ns - 36 - ns - 12 - ns Min. Typ. Max. Unit 1.2 V 1 Table 5: Dynamic Symbol Ciss Parameter Test conditions Input capacitance VDS = 25 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VDD = 15 V, ID = 80 A, VGS = 4.5 V (see Figure 14: "Test circuit for gate charge behavior") pF nC Table 6: Switching times Symbol td(on) tr td(off) tf Parameter Test conditions Turn-on delay time VDD = 15 V, ID = 40 A, RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times") Rise time Turn-off delay time Fall time Table 7: Source-drain diode Symbol VSD(1) Parameter Test conditions Forward on voltage ISD = 80 A, VGS = 0 V - trr Reverse recovery time - Qrr Reverse recovery charge IRRM Reverse recovery current ID = 80 A, di/dt = 100 A/µs VDD = 24 V (see Figure 15: "Test circuit for inductive load switching and diode recovery times") Notes: (1)Pulsed: 4/15 pulse duration = 300 µs, duty cycle 1.5% DocID029591 Rev 2 - 21 14 1.3 ns nC A STD80N3LL 2.1 Electrical characteristics Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID029591 Rev 2 5/15 Electrical characteristics STD80N3LL Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Source-drain diode forward characteristics 6/15 DocID029591 Rev 2 STD80N3LL 3 Test circuits Test circuits Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform DocID029591 Rev 2 7/15 Package information 4 STD80N3LL Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 8/15 DocID029591 Rev 2 STD80N3LL 4.1 Package information DPAK package information Figure 19: DPAK (TO-252) type A2 package outline 0068772_type-A2_rev21 DocID029591 Rev 2 9/15 Package information STD80N3LL Table 8: DPAK (TO-252) type A2 mechanical data mm Dim. Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 5.10 5.20 5.30 e 2.16 2.28 2.40 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 L1 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 10/15 Typ. 5.10 5.25 6.60 1.00 0.20 0° DocID029591 Rev 2 8° STD80N3LL Package information Figure 20: DPAK (TO-252) type A2 recommended footprint (dimensions are in mm) DocID029591 Rev 2 11/15 Package information 4.2 STD80N3LL DPAK (TO-252) packing information Figure 21: DPAK (TO-252) tape outline 12/15 DocID029591 Rev 2 STD80N3LL Package information Figure 22: DPAK (TO-252) reel outline Table 9: DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 B1 D 1.5 D1 1.5 E 1.65 F 1.6 Min. Max. 330 13.2 D 20.2 G 16.4 1.85 N 50 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 DocID029591 Rev 2 18.4 22.4 13/15 Revision history 5 STD80N3LL Revision history Table 10: Document revision history Date Revision 26-Jul-2016 1 First release. 2 Document status promoted from preliminary to production data. Updated Section 2: "Electrical characteristics" and added Section 2.1: "Electrical characteristics (curves)". Minor text changes. 06-Dec-2016 14/15 Changes DocID029591 Rev 2 STD80N3LL IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID029591 Rev 2 15/15