STD80N6F7

STD80N6F7 Datasheet N-channel 60 V, 6.8 mΩ typ., 40 A STripFET™ F7 Power MOSFET in a DPAK package Features TAB 2 3 1 DPAK D(2, TAB) Order code VDS RDS(on ) max. ID STD80N6F7 60 V 8.0 mΩ 40 A • Among the lowest RDS(on) on the market • • Excellent FoM (figure of merit) Low Crss/Ciss ratio for EMI immunity • High avalanche ruggedness Applications G(1) • S(3) AM01475v1_noZen Switching applications Description This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low on-state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. Product status STD80N6F7 Product summary Order code STD80N6F7 Marking 80N6F7 Package DPAK Packing Tape and reel DS11885 - Rev 5 - February 2018 For further information contact your local STMicroelectronics sales office. www.st.com/ STD80N6F7 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 60 V VGS Gate-source voltage ±20 V ID (1) Drain current (continuous) at TC = 25 °C 40 A Drain current (continuous) at TC = 100 °C 40 A Drain current (pulsed) 160 A Total dissipation at TC = 25 °C 100 W Single pulse avalanche energy 60 mJ Peak diode recovery 4.3 V/ns -55 to 175 °C ID (1) IDM (2) (1) PTOT EAS (3) dv/dt(4) Tj Tstg Operating junction temperature range Storage temperature range 1. This value is limited by package 2. Pulse width limited by safe operating area 3. Starting Tj =25 °C, IAS=20 A, VDD=40 V. 4. ISD = 20 A, di/dt= 700A/µs, VDD =48 V. Table 2. Thermal data Symbol Parameter Value Unit Rthj-pcb (1) Thermal resistance junction-pcb 50 °C/W Rthj-case Thermal resistance junction-case 1.5 °C/W 1. When mounted on FR-4 board of 1 inch², 2oz Cu , t < 10 s DS11885 - Rev 5 page 2/14 STD80N6F7 Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified Table 3. On/off-state Symbol Parameter Test conditions Min. Typ. Max. Unit Drain-source breakdown voltage VGS = 0 V, ID = 1 mA IDSS Zero gate voltage drain current VGS = 0 V, VDS = 60 V 1 µA IGSS Gate-body leakage current VGS = 20 V, VDS = 0 V 100 nA VGS(th) Gate threshold voltage VDD = VGS, ID = 250 µA 4 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 20 A 6.8 8.0 mΩ Min. Typ. Max. Unit - 1600 - pF - 800 - pF - 50 - pF V(BR)DSS 60 V 2 Table 4. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge VDD = 30 V, ID = 20 A, - 25 - nC Qgs Gate-source charge VGS= 0 to 10 V - 7.2 - nC Qgd Gate-drain charge (see Figure 13. Test circuit for gate charge behavior) - 8 - nC Min. Typ. Max. Unit - 15 - ns - 17.6 - ns - 24.4 - ns - 7.8 - ns Min. Typ. Max. Unit 1.2 V VDS = 30 V, f = 1 MHz, VGS = 0 V Table 5. Switching times Symbol td(on) tr td(off) tf Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD= 30 V, ID = 20 A, RG = 4.7 Ω, VGS = 10 V (see Figure 12. Test circuit for resistive load switching times and Figure 17. Switching time waveform) Table 6. Source-drain diode Symbol VSD (1) Parameter Test conditions Forward on voltage ISD = 40 A, VDD = 0 V trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ID = 40 A, di/dt = 100 A/μs ,VDD = 48 V (see Figure 14. Test circuit for inductive load switching and diode recovery times) - 39.6 ns - 36 nC - 1.8 A 1. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DS11885 - Rev 5 page 3/14 STD80N6F7 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Normalized thermal impedance GADG030320171349SOA ID (A) Operation in this area is limited by R DS(on) K GADG030320171349ZTH δ = 0.5 10 2 δ = 0.2 tp =10 µs 10 1 δ = 0.1 δ = 0.05 10 -1 δ = 0.02 tp =100 µs 10 0 δ = 0.01 T j ≤ 175 °C T c = 25°C single pulse Single pulse tp =1 ms tp =10 ms 10 -1 10 -1 10 VDS (V) 10 1 0 10 -2 10 -5 Figure 3. Output characteristics ID (A) 10 -3 10 -2 tp (s) Figure 4. Transfer characteristics GADG030320171349OCH VGS = 8, 9, 10 V VGS = 7 V 100 10 -4 ID (A) GADG030320171349TCH 140 VGS = 6 V VDS = 6 V 120 80 100 60 80 60 VGS = 5 V 40 40 20 2 4 6 8 VDS (V) Figure 5. Gate charge vs gate-source voltage VGS (V) TJ = 175 °C 20 VGS = 4 V 0 0 TJ = 25 °C GADG030320171350QVG 12 0 2 TJ = -55 °C 3 10 5 6 VGS (V) Figure 6. Static drain-source on-resistance RDS(on) (mΩ) GADG030320171350RID 9 VDS = 30 V ID = 20 A 4 VGS = 10 V 8 8 7 6 6 4 5 2 0 0 DS11885 - Rev 5 5 10 15 20 25 Qg (nC) 4 0 10 20 30 40 ID (A) page 4/14 STD80N6F7 Electrical characteristics (curves) Figure 7. Capacitance variations C (pF) Figure 8. Normalized VGS(th) vs temperature GADG030320171447CVR VGS(th) (norm.) f = 1 MHz GADG030320171447VTH ID = 250 µA 1.2 CISS 10 3 1 COSS 0.8 10 2 0.6 0.4 CRSS 10 1 0 10 20 30 40 50 60 0.2 -75 VDS (V) Figure 9. Normalized on-resistance vs temperature RDS(on) (norm.) 75 V(BR)DSS (norm.) 125 175 Tj (°C) GADG030320171448BDV 1.08 VGS = 10 V ID = 20 A 1.6 25 Figure 10. Normalized V(BR)DSS vs temperature GADG030320171448RON 2 -25 ID = 1 mA 1.04 1.2 1 0.8 0.96 0.4 0 -75 -25 25 75 125 175 0.92 -75 Tj (°C) -25 25 75 125 175 Tj (°C) Figure 11. Source-drain diode forward characteristics VSD (V) GADG030320171449SDF 1.1 1 0.9 TJ = -55 °C TJ = 25 °C 0.8 TJ = 175 °C 0.7 0.6 0 DS11885 - Rev 5 10 20 30 40 ISD (A) page 5/14 STD80N6F7 Test circuits 3 Test circuits Figure 12. Test circuit for resistive load switching times Figure 13. Test circuit for gate charge behavior VDD RL RL 2200 + μF 3.3 μF VDD VD + pulse width RG VGS IG= CONST VGS 2.7 kΩ 2200 μF D.U.T. D.U.T. 100 Ω VG 47 kΩ pulse width 1 kΩ AM01469v10 AM01468v1 Figure 14. Test circuit for inductive load switching and diode recovery times Figure 15. Unclamped inductive load test circuit L D G A D.U.T. S 25 Ω A A 100 µH fast diode B B B VD 3.3 µF D G + RG 1000 + µF 2200 + µF 3.3 µF VDD ID VDD D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 16. Unclamped inductive waveform Figure 17. Switching time waveform V(BR)DSS VD ton td(on) IDM toff td(off) tr 90% 90% 10% ID VDD tf VDD 10% 0 VGS AM01472v1 0 VDS 90% 10% AM01473v1 DS11885 - Rev 5 page 6/14 STD80N6F7 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS11885 - Rev 5 page 7/14 STD80N6F7 DPAK (TO-252) type A2 package information 4.1 DPAK (TO-252) type A2 package information Figure 18. DPAK (TO-252) type A2 package outline 0068772_type-A2_rev24 DS11885 - Rev 5 page 8/14 STD80N6F7 DPAK (TO-252) type A2 package information Table 7. DPAK (TO-252) type A2 mechanical data Dim. mm Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 5.10 5.20 5.30 e 2.16 2.28 2.40 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 L1 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 DS11885 - Rev 5 Typ. 5.10 5.25 6.60 1.00 0.20 0° 8° page 9/14 STD80N6F7 DPAK (TO-252) type C2 package information 4.2 DPAK (TO-252) type C2 package information Figure 19. DPAK (TO-252) type C2 package outline 0068772_C2_24 Table 8. DPAK (TO-252) type C2 mechanical data Dim. DS11885 - Rev 5 mm Min. Typ. Max. A 2.20 2.30 2.38 A1 0.90 1.01 1.10 A2 0.00 0.10 b 0.72 0.85 b4 5.13 5.33 5.46 page 10/14 STD80N6F7 DPAK (TO-252) footprint information Dim. mm Min. Max. c 0.47 0.60 c2 0.47 0.60 D 6.00 D1 5.10 E 6.50 E1 5.20 e 2.186 2.286 2.386 H 9.80 10.10 10.40 L 1.40 1.50 1.70 L1 L2 L4 6.10 6.20 5.60 6.60 6.70 5.50 2.90 REF 0.90 L3 1.25 0.51 BSC 0.60 L6 4.3 Typ. 0.80 1.00 1.80 BSC θ1 5° 7° 9° θ2 5° 7° 9° V2 0° 8° DPAK (TO-252) footprint information Figure 20. DPAK (TO-252) recommended footprint (dimensions are in mm) FP_0068772_24 DS11885 - Rev 5 page 11/14 STD80N6F7 Revision history Table 9. Document revision history Date Revision Changes 03-Nov-2016 1 First release 03-Mar-2017 2 Updated Table 2: "Absolute maximum ratings" and Table 5: "Dynamic". Added Section 2.1: "Electrical characteristics (curves)". Minor text changes. 02-May-2017 3 Updated Table 2: "Absolute maximum ratings". 01-Feb-2018 4 Added DPAK (TO-252) type C package information. Removed maturity status indication from cover page. 12-Feb-2018 DS11885 - Rev 5 5 Modified Section 4 Package information. Minor text changes. page 12/14 STD80N6F7 Contents Contents 1 Electrical ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 DPAK (TO-252) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 DPAK (TO-252) type C2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 DPAK (TO-252) footprint information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 DS11885 - Rev 5 page 13/14 STD80N6F7 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS11885 - Rev 5 page 14/14