STD8N80K5

STD8N80K5 Datasheet N-channel 800 V, 0.8 Ω typ., 6 A MDmesh™ K5 Power MOSFET in a DPAK package Features TAB 2 3 1 DPAK D(2, TAB) Order code VDS RDS(on ) max. ID PTOT STD8N80K5 800 V 0.95 Ω 6A 110 W • Industry’s lowest RDS(on) x area • • • • Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Applications G(1) • S(3) AM01475V1 Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Product status STD8N80K5 Product summary Order code STD8N80K5 Marking 8N80K5 Package DPAK Packing Tape and reel DS9561 - Rev 3 - August 2018 For further information contact your local STMicroelectronics sales office. www.st.com STD8N80K5 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ±30 V ID Drain current (continuous) at TC = 25 °C 6 A ID Drain current (continuous) at TC = 100 °C 4 A IDM (1) Drain current pulsed 24 A PTOT Total dissipation at TC = 25 °C 110 W dv/dt (2) Peak diode recovery voltage slope 4.5 dv/dt (3) MOSFET dv/dt ruggedness 50 Tj Operating junction temperature range Tstg V/ns - 55 to 150 °C Value Unit Thermal resistance junction-case 1.14 °C/W Thermal resistance junction-pcb 50 °C/W Value Unit 2 A 114 mJ Storage temperature range 1. Pulse width limited by safe operating area. 2. ISD≤ 6 A, di/dt ≤ 100 A/μs; VDS peak ≤ V(BR)DSS 3. VDS ≤ 640 V Table 2. Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter 1. When mounted on 1inch² FR-4 board, 2 oz Cu Table 3. Avalanche characteristics Symbol IAR EAS DS9561 - Rev 3 Parameter Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax.) Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR, VDD = 50 V) page 2/19 STD8N80K5 Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified Table 4. On/off-state Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions VGS = 0 V, ID = 1 mA Min. Typ. 800 IDSS 1 µA 50 µA ±10 µA 4 5 V 0.8 0.95 Ω Min. Typ. Max. Unit - 450 - pF - 50 - pF - 1 - pF - 57 - pF 24 - pF VGS = 0 V, VDS = 800 V TC = 125 °C (1) IGSS Gate body leakage current VDS = 0 V, VGS = ±20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 3 A Unit V VGS = 0 V, VDS = 800 V Zero gate voltage drain current Max. 3 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr) (1) Equivalent capacitance time related Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V VDS = 0 to 640 V, VGS = 0 V Co(er) (2) Equivalent capacitance energy related Rg Intrinsic gate resistance f = 1 MHz , ID = 0 A - 6 - Ω Qg Total gate charge VDD = 640 V, ID = 6 A - 16.5 - nC Qgs Gate-source charge VGS = 0 to 10 V - 3.2 - nC Gate-drain charge (see Figure 15. Test circuit for gate charge behavior ) - 11 - nC Qgd 1. Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. 2. Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS9561 - Rev 3 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. Unit VDD = 400 V, ID = 3 A, RG = 4.7 Ω, VGS = 10 V (see Figure 14. Test circuit for resistive load switching times and Figure 19. Switching time waveform) - 12 - ns - 14 - ns - 32 - ns - 20 - ns page 3/19 STD8N80K5 Electrical characteristics Table 7. Source-drain diode Symbol ISD ISDM (1) (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 6 A Source-drain current (pulsed) - 24 A 1.5 V Forward on voltage ISD = 6 A, VGS = 0 V - trr Reverse recovery time ISD = 6 A, di/dt = 100 A/µs, - 300 ns Qrr Reverse recovery charge - 3 µC IRRM Reverse recovery current VDD = 60 V, see Figure 16. Test circuit for inductive load switching and diode recovery times) - 20 A VSD trr Reverse recovery time ISD = 6 A, di/dt = 100 A/µs, - 415 ns Qrr Reverse recovery charge VDD = 60 V, Tj = 150 °C - 3.8 µC IRRM Reverse recovery current (see Figure 16. Test circuit for inductive load switching and diode recovery times) - 18 A Min. Typ. Max Unit ±30 - - V 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%. Table 8. Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS = ±1 mA, ID = 0 A The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry. DS9561 - Rev 3 page 4/19 STD8N80K5 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance AM15630v1 ID (A) 10µs 10 in 1 s ai re limit(on) aRon S DR ax is th 100µs n m tio by ra pe ited O im L 1ms 10-1 Tj=150°C Tc=25°C Single pulse 0.01 1 0.1 10 10-2 10-5 VDS(V) 100 Figure 3. Output characteristics VGS=10, 11V 12 10-4 10-3 10-2 tp (s) 10-1 Figure 4. Transfer characteristics AM15633v1 ID (A) AM15634v1 ID (A) VDS=20V 12 9V 10 10 8 8 8V 6 6 4 4 7V 2 2 6V 0 100 10ms 0.1 0 4 8 12 16 VDS(V) Figure 5. Gate charge vs. gate-source voltage VGS (V) VDS AM15635v1 VDS VDD=640V ID=6A 12 (V) 600 10 500 8 400 6 300 4 200 2 100 0 DS9561 - Rev 3 GC20460 K 0 4 8 12 16 0 Qg (nC) 0 5 6 7 8 9 10 VGS(V) Figure 6. Static drain-source on-resistance AM15636v1 RDS(on) (Ω) VGS=10V 1.6 1.2 0.8 0.4 0 1 2 3 4 5 6 ID(A) page 5/19 STD8N80K5 Electrical characteristics (curves) Figure 7. Capacitance variations Figure 8. Source-drain diode forward characteristics AM15637v1 C (pF) AM15641v1 VSD (V) TJ=-50°C 0.9 1000 Ciss TJ=25°C 0.8 100 0.7 Coss 10 Crss 1 0.1 1 10 100 VDS(V) Figure 9. Normalized gate threshold voltage vs. temperature AM15639v1 VGS(th) (norm) ID=100µA VDS=VGS TJ=150°C 0.6 0.5 1 2 5 ISD(A) Figure 10. Normalized on-resistance vs. temperature AM15640v1 RDS(on) (norm) VGS=10V ID=3 A 2.4 1 4 3 2 1.6 0.8 1.2 0.6 0.4 -50 0.8 0 50 100 TJ(°C) Figure 11. Normalized V(BR)DSS vs. temperature AM15642v1 V(BR)DSS (norm) 1.1 1.02 60 0.98 40 0.94 20 100 TJ(°C) 100 TJ(°C) AM15643v1 EAS (mJ) 80 50 50 VDD=50V ID=2A 100 ID = 1mA 0 0 Figure 12. Maximum avalanche energy vs. starting TJ 1.06 0.9 -50 DS9561 - Rev 3 0.4 -50 0 0 40 80 120 TJ(°C) page 6/19 STD8N80K5 Electrical characteristics (curves) Figure 13. Output capacitance stored energy AM15638v1 Eoss (µJ) 6 4 2 0 0 DS9561 - Rev 3 200 400 600 VDS(V) page 7/19 STD8N80K5 Test circuits 3 Test circuits Figure 14. Test circuit for resistive load switching times Figure 15. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 16. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 17. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 19. Switching time waveform Figure 18. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS9561 - Rev 3 page 8/19 STD8N80K5 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS9561 - Rev 3 page 9/19 STD8N80K5 DPAK (TO-252) type A2 package information 4.1 DPAK (TO-252) type A2 package information Figure 20. DPAK (TO-252) type A2 package outline 0068772_type-A2_rev25 DS9561 - Rev 3 page 10/19 STD8N80K5 DPAK (TO-252) type A2 package information Table 9. DPAK (TO-252) type A2 mechanical data Dim. mm Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 5.10 5.20 5.30 e 2.159 2.286 2.413 e1 4.445 4.572 4.699 H 9.35 10.10 L 1.00 1.50 L1 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 DS9561 - Rev 3 Typ. 5.10 5.25 6.60 1.00 0.20 0° 8° page 11/19 STD8N80K5 DPAK (TO-252) type C2 package information 4.2 DPAK (TO-252) type C2 package information Figure 21. DPAK (TO-252) type C2 package outline 0068772_C2_25 DS9561 - Rev 3 page 12/19 STD8N80K5 DPAK (TO-252) type C2 package information Table 10. DPAK (TO-252) type C2 mechanical data Dim. mm Min. Typ. Max. A 2.20 2.30 2.38 A1 0.90 1.01 1.10 A2 0.00 0.10 b 0.72 0.85 b4 5.13 c 0.47 0.60 c2 0.47 0.60 D 6.00 D1 5.10 E 6.50 E1 5.20 e 2.186 2.286 2.386 H 9.80 10.10 10.40 L 1.40 1.50 1.70 L1 L2 6.20 5.60 6.60 6.70 5.50 0.90 1.25 0.51 BSC 0.60 L6 DS9561 - Rev 3 6.10 5.46 2.90 REF L3 L4 5.33 0.80 1.00 1.80 BSC θ1 5° 7° 9° θ2 5° 7° 9° V2 0° 8° page 13/19 STD8N80K5 DPAK (TO-252) type C2 package information Figure 22. DPAK (TO-252) recommended footprint (dimensions are in mm) FP_0068772_25 DS9561 - Rev 3 page 14/19 STD8N80K5 DPAK (TO-252) packing information 4.3 DPAK (TO-252) packing information Figure 23. DPAK (TO-252) tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 K0 For machine ref. only including draft and radii concentric around B0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 DS9561 - Rev 3 page 15/19 STD8N80K5 DPAK (TO-252) packing information Figure 24. DPAK (TO-252) reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 11. DPAK (TO-252) tape and reel mechanical data Tape Dim. mm mm Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 DS9561 - Rev 3 Reel Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 18.4 22.4 page 16/19 STD8N80K5 Revision history Table 12. Document revision history DS9561 - Rev 3 Date Revision Changes 23-Mar-2013 1 First release. Part number previously included in datasheet DM00062075 29-Mar-2013 2 Added: MOSFET dv/dt ruggedness on Table 2 20-Aug-2018 3 Updated Section 4 Package information. Minor text changes. page 17/19 STD8N80K5 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.1 DPAK (TO-252) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 DPAK (TO-252) type C2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 DS9561 - Rev 3 page 18/19 STD8N80K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS9561 - Rev 3 page 19/19