STD9N80K5

STD9N80K5 Datasheet N-channel 800 V, 0.73 Ω typ., 7 A MDmesh™ K5 Power MOSFET in a DPAK package Features TAB 2 3 1 • • • • • DPAK D ( 2 , TAB ) Order code VDS RDS(on)max. ID PTOT STD9N80K5 800 V 0.90 Ω 7A 110 W Industry’s lowest RDS(on) x area Industry’s best figure of merit (FoM) Ultra-low gate charge 100% avalanche tested Zener-protected Applications G( 1) • AM15572V1 S(3) Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Product status STD9N80K5 Product summary Order code STD9N80K5 Marking 9N80K5 Package DPAK Packing Tape and reel DS11297 - Rev 3 - November 2018 For further information contact your local STMicroelectronics sales office. www.st.com STD9N80K5 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter VGS Gate-source voltage Value Unit ±30 V ID Drain current (continuous) at TC = 25 °C 7 A ID Drain current (continuous) at TC = 100 °C 4.4 A ID (1) Drain current (pulsed) 28 A PTOT Total power dissipation at TC = 25 °C 110 W dv/dt(2) Peak diode recovery voltage slope 4.5 V/ns dv/dt(3) MOSFET dv/dt ruggedness 50 V/ns Tstg Storage temperature range - 55 to 150 °C Tj Operating junction temperature range 1. Pulse width limited by safe operating area. 2. ISD ≤ 7 A, di/dt ≤ 100 A/µs; VDS( peak) < V(BR)DSS; VDD= 640 V 3. VDS ≤ 640 V Table 2. Thermal data Symbol Parameter Rthj-case Rthj-pcb (1) Value Unit Thermal resistance junction-case 1.14 °C/W Thermal resistance junction-pcb 50 °C/W 1. When mounted on FR-4 board of 1 inch², 2 oz Cu Table 3. Avalanche characteristics Symbol DS11297 - Rev 3 Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 2.4 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR; VDD = 50 V) 200 mJ page 2/19 STD9N80K5 Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified Table 4. On/off states Symbol Parameter V(BR)DSS Drain-source breakdown voltage IDSS Zero gate voltage Drain current IGSS Test conditions VGS = 0 V, ID = 1 mA Min. Typ. Max. Unit 800 V VGS = 0 V, VDS = 800 V 1 µA VGS = 0 V, VDS = 800 V, TC = 125 °C (1) 50 µA Gate-body leakage current VDS = 0 V, VGS = ±20 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID =100 µA 4 5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 3.5 A 0.73 0.90 Ω 3 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V Co(tr) (1) Equivalent capacitance time related Co(er) (2) Equivalent capacitance energy related VDS = 0 to 640 V, VGS = 0 V Min. Typ. Max. Unit - 340 - pF - 37 - pF - 0.65 - pF - 61 - pF - 22 - pF Rg Intrinsic gate resistance f = 1 MHz , ID= 0 A - 7 - Ω Qg Total gate charge VDD = 640 V, ID = 7 A - 12 - nC Qgs Gate-source charge VGS= 0 to 10 V - 3.8 - nC Qgd Gate-drain charge See (Figure 15. Test circuit for gate charge behavior) - 6.7 - nC 1. Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. 2. Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS Table 6. Switching times Symbol td(on) tr td(off) tf DS11297 - Rev 3 Parameter Turn-on delay time Test conditions Min. Typ. Max. Unit - 11 - ns VDD= 400 V, ID =3.5 A, RG = 4.7 Ω Rise time VGS = 10 V - 5.7 - ns Turn-off delay time See (Figure 14. Test circuit for resistive load switching times and Figure 19. Switching time waveform) - 65.3 - ns - 13.6 - ns Fall time page 3/19 STD9N80K5 Electrical characteristics Table 7. Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 7 A ISDM (1) Source-drain current (pulsed) - 28 A VSD (2) Forward on voltage ISD = 7 A, VGS = 0 V - 1.5 V Reverse recovery time - 292 ns - 2.66 µC - 18.2 A - 477 ns - 3.91 µC - 16.4 A ISD trr Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 7 A, di/dt = 100 A/µs,VDD = 60 V See Figure 16. Test circuit for inductive load switching and diode recovery times ISD = 7 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C See Figure 16. Test circuit for inductive load switching and diode recovery times 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 8. Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS = ±1 mA, ID = 0 A Min. ±30 Typ. Max. - Unit V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry. DS11297 - Rev 3 page 4/19 STD9N80K5 STD9N80K5_Electrical characteristics curves 2.1 STD9N80K5_Electrical characteristics curves Figure 2. Thermal impedance Figure 1. Safe operating area GIPD280120161003SOA ID (A) Operation in this area is limited by R DS(on) tp = 10µs 10 1 tp = 100µs 10 0 100 tp = 1ms tp = 10ms 10 GC20460 K 10-1 -1 10 -2 10 -1 T j ≤150 °C T c = 25°C single pulse 10 0 10 1 10 2 10 3 VDS (V) Figure 3. Output characteristics ID (A) VGS = 11 V 10 VGS = 10 V 10-4 10-3 10-2 GIPG101115VK82FTCH 12 VGS = 9 V tp (s) 10-1 Figure 4. Transfer characteristics ID (A) GIPG101115VK82FOCH 12 10-2 10-5 VDS =20 V 10 8 8 VGS = 8 V 6 6 4 4 VGS = 7 V 2 2 VGS = 6 V 0 0 4 8 12 16 VDS (V) Figure 5. Gate charge vs gate-source voltage VGS (V) GIPG101115VK82FQVG VDS (V) VDS 12 VDD = 640 V ID = 3.5 A 600 0 4 5 6 7 8 9 VGS (V) Figure 6. Static drain-source on-resistance R DS(on) (Ω) GIPG101115VK82FRID V GS = 10 V 0.97 10 500 8 400 6 300 4 200 2 100 0.65 0 Qg (nC) 0.57 0 0.89 0.81 0 0 DS11297 - Rev 3 2 4 6 8 10 12 0.73 1 2 3 4 5 6 I D (A) page 5/19 STD9N80K5 STD9N80K5_Electrical characteristics curves Figure 7. Capacitance variations C (pF) GIPG101115VK82FCVR Figure 8. Normalized gate threshold voltage vs temperature V GS(th) (norm.) 10 3 CISS 10 2 GIPG101115VK82FVTH I D = 100 µA 1.2 1.0 COSS 10 1 0.8 CRSS f = 1 MHz 10 0 10 -1 10 -1 0.6 10 0 10 1 10 2 VDS (V) Figure 9. Normalized on-resistance vs temperature RDS(on) (norm.) GIPG101115VK82FRON VGS = 10 V 2.6 0.4 -75 1.04 1.4 1.0 1 0.96 0.6 0.92 75 125 Tj (°C) Figure 11. Output capacitance stored energy EOSS (µJ) GIPG101115VK82FEOS 6 T j (°C) ID = 1 mA 0.88 -75 -25 25 75 125 Tj (°C) Figure 12. Source-drain diode forward characteristics VSD (V) GIPG101115VK82FSDF 1.0 5 125 GIPG101115VK82FBDV 1.12 1.8 25 75 V(BR)DSS (norm.) 1.08 -25 25 Figure 10. Normalized V(BR)DSS vs temperature 2.2 0.2 -75 -25 Tj = -50 °C 0.9 4 Tj = 25 °C 0.8 3 0.7 2 0.6 1 0 0 DS11297 - Rev 3 Tj = 150 °C 100 200 300 400 500 600 700 VDS (V) 0.5 1 2 3 4 5 6 7 ISD (A) page 6/19 STD9N80K5 STD9N80K5_Electrical characteristics curves Figure 13. Maximum avalanche energy vs starting TJ EAS (mJ) GIPG101115VK82FEAS 200 160 120 80 40 0 -75 DS11297 - Rev 3 Single pulse, ID=2.4 A, VDD=50 V -25 25 75 125 TJ(°C) page 7/19 STD9N80K5 Test circuits 3 Test circuits Figure 14. Test circuit for resistive load switching times Figure 15. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 16. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 17. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 19. Switching time waveform Figure 18. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS11297 - Rev 3 page 8/19 STD9N80K5 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS11297 - Rev 3 page 9/19 STD9N80K5 DPAK (TO-252) type A2 package information 4.1 DPAK (TO-252) type A2 package information Figure 20. DPAK (TO-252) type A2 package outline 0068772_type-A2_rev25 DS11297 - Rev 3 page 10/19 STD9N80K5 DPAK (TO-252) type A2 package information Table 9. DPAK (TO-252) type A2 mechanical data Dim. mm Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 5.10 5.20 5.30 e 2.159 2.286 2.413 e1 4.445 4.572 4.699 H 9.35 10.10 L 1.00 1.50 L1 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 DS11297 - Rev 3 Typ. 5.10 5.25 6.60 1.00 0.20 0° 8° page 11/19 STD9N80K5 DPAK (TO-252) type C2 package information 4.2 DPAK (TO-252) type C2 package information Figure 21. DPAK (TO-252) type C2 package outline 0068772_C2_25 DS11297 - Rev 3 page 12/19 STD9N80K5 DPAK (TO-252) type C2 package information Table 10. DPAK (TO-252) type C2 mechanical data Dim. mm Min. Typ. Max. A 2.20 2.30 2.38 A1 0.90 1.01 1.10 A2 0.00 0.10 b 0.72 0.85 b4 5.13 c 0.47 0.60 c2 0.47 0.60 D 6.00 D1 5.10 E 6.50 E1 5.20 e 2.186 2.286 2.386 H 9.80 10.10 10.40 L 1.40 1.50 1.70 L1 L2 6.20 5.60 6.60 6.70 5.50 0.90 1.25 0.51 BSC 0.60 L6 DS11297 - Rev 3 6.10 5.46 2.90 REF L3 L4 5.33 0.80 1.00 1.80 BSC θ1 5° 7° 9° θ2 5° 7° 9° V2 0° 8° page 13/19 STD9N80K5 DPAK (TO-252) type C2 package information Figure 22. DPAK (TO-252) recommended footprint (dimensions are in mm) FP_0068772_25 DS11297 - Rev 3 page 14/19 STD9N80K5 DPAK (TO-252) packing information 4.3 DPAK (TO-252) packing information Figure 23. DPAK (TO-252) tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 K0 For machine ref. only including draft and radii concentric around B0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 DS11297 - Rev 3 page 15/19 STD9N80K5 DPAK (TO-252) packing information Figure 24. DPAK (TO-252) reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 11. DPAK (TO-252) tape and reel mechanical data Tape Dim. mm mm Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 DS11297 - Rev 3 Reel Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 18.4 22.4 page 16/19 STD9N80K5 Revision history Table 12. Document revision history Date 20-Oct-2015 Revision Changes 1 First release. Document status promoted from preliminary to production data. 28-Jan-2016 2 Updated DPAK (TO-252) type A2 package information. Inserted Section 2 Electrical characteristics. Minor text changes. 12-Nov-2018 DS11297 - Rev 3 3 Updated , , Table 5. Dynamic and Table 7. Source-drain diode. Added Section 4.2 DPAK (TO-252) type C2 package information. page 17/19 STD9N80K5 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 STD9N80K5_Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.1 DPAK (TO-252) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 DPAK (TO-252) type C2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 DS11297 - Rev 3 page 18/19 STD9N80K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS11297 - Rev 3 page 19/19