STDLED625H

STDLED625H N-channel 620 V, 1.7 Ω, 4.5 A Power MOSFET in a DPAK package Datasheet − preliminary data Features TAB Order code VDS RDS(on) max STDLED625H 620 V 2Ω ) s ( ct 4.5 A • 100% avalanche tested 3 PTOT ID 70 W u d o • Extremely high dv/dt capability 1 • Gate charge minimized DPAK r P e • Very low intrinsic capacitance • Improved diode reverse recovery characteristics t e l o • Zener-protected Figure 1. Internal schematic diagram )- s ( t c u d o G(1) r P e t e l o bs s b O Applications D(2,TAB) • LED lighting applications Description These Power MOSFETs boast extremely low onresistance and very good dv/dt capability, rendering them suitable for buck-boost and flyback topologies. S(3) AM01476v1 O Table 1. Device summary Order code Marking Package Packaging STDLED625H LED625H DPAK Tape and reel March 2013 DocID024435 Rev 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/17 www.st.com 17 Contents STDLED625H Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuits .............................................. 9 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 2/17 DocID024435 Rev 1 STDLED625H 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 620 V VGS Gate- source voltage ± 30 V ID Drain current (continuous) at TC = 25 °C 4.5 A ID Drain current (continuous) at TC = 100 °C 2.3 A Drain current (pulsed) 18.0 A IDM (1) PTOT Total dissipation at TC = 25 °C 70 IAR Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max) 3.8 EAS Single pulse avalanche energy (starting Tj = 25°C, ID = IAR, VDD = 50V) VESD(G-S) Gate source ESD(HBM-C = 100 pF, R = 1.5 kΩ) dv/dt (2) Peak diode recovery voltage slope so b O VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 °C) Tstg Storage temperature Tj ) (s e t e l ct Max. operating junction temperature u d o W du o r P 115 ) s ( ct A mJ 2500 V 12 V/ns V - 55 to 150 °C 150 °C 1. Pulse width limited by safe operating area. 2. ISD ≤ 3.8 A, di/dt = 400 A/µs, VDD = 80% V(BR)DSS, VDS peak ≤ V(BR)DSS. r P e t e l o Symbol s b O Rthj-case Table 3. Thermal data Parameter Thermal resistance junction-case max Rthj-pcb (1) Thermal resistance junction-pcb max Value Unit 1.79 °C/W 50 °C/W 1. When mounted on 1inch² FR-4 board, 2 oz Cu. DocID024435 Rev 1 3/17 Electrical characteristics 2 STDLED625H Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4. On /off states Symbol Parameter Drain-source breakdown voltage V(BR)DSS IDSS Zero gate voltage drain current IGSS Gate-body leakage current Test conditions VGS = 0, ID = 1 mA Min. Typ. Max. 620 V VGS = 0, VDS = 620V 1 50 µA ± 10 µA 3.6 4.5 V 1.7 2 Ω Min. Typ. Max. Unit c u d VDS = 0, VGS = ± 20 V Gate threshold voltage VDS = VGS, ID = 50 µA RDS(on Static drain-source onVGS = 10 V, ID = 1.9 A resistance e t e ol s b O µA ) s ( t VGS = 0 VDS = 620V, TC=125 °C VGS(th) Unit o r P 3 Table 5. Dynamic Symbol Parameter Input capacitance Output capacitance Reverse transfer capacitance VDS = 50 V, f = 1 MHz, VGS = 0 - 560 43 7.5 - pF pF pF Equivalent output capacitance VDS = 0 to 496 V, VGS = 0 - 27 - pF RG Intrinsic gate resistance f = 1 MHz open drain 2 5 10 Ω Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD = 496 V, ID = 3.8 A, VGS = 10 V (see Figure 16) - 23 4 13 - nC nC nC Ciss Coss Crss Coss eq.(1) t c u d o r P e t e l o s b O ) (s Test conditions 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS Table 6. Switching times Symbol td(on) tr td(off) tf 4/17 Parameter Turn-on delay time Rise time Turn-off-delay time Fall time Test conditions VDD = 300 V, ID = 1.9 A, RG = 4.7 Ω, VGS = 10 V (see Figure 15) DocID024435 Rev 1 Min. Typ. - 10 9 29 19 Max. Unit - ns ns ns ns STDLED625H Electrical characteristics Table 7. Source drain diode Symbol Parameter ISD ISDM (1) Source-drain current Source-drain current (pulsed) VSD (2) Forward on voltage trr Qrr IRRM trr Qrr IRRM Test conditions Min. Typ. Max. Unit - 3.8 15.2 A A ISD = 3.8 A, VGS = 0 - 1.6 V Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 3.8 A, di/dt = 100 A/µs VDD = 60 V (see Figure 20) - 220 1.4 13 ns µC A Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 3.8 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C (see Figure 20) - 270 1.9 14 ns µC A 1. Pulse width limited by safe operating area. ) s ( ct u d o 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5% r P e Table 8. Gate-source Zener diode Symbol V(BR)GSO Parameter t e l o Test conditions Gate-source breakdown voltage bs IGS= ± 1 mA, ID=0 Min. Typ. 30 - Max. Unit - V O ) The built-in back-to-back Zener diodes have been specifically designed to enhance not only the device’s ESD capability, but also to make them capable of safely absorbing any voltage transients that may occasionally be applied from gate to source. In this respect, the Zener voltage is appropriate to achieve efficient and cost-effective protection of device integrity. The integrated Zener diodes thus eliminate the need for external components. s ( t c u d o r P e t e l o s b O DocID024435 Rev 1 5/17 Electrical characteristics 2.1 STDLED625H Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance AM07173v1 10 10µs is ID (A) D S( on ) O Li per m at ite io d ni by n m this ax a R rea 100µs 1 1ms 10ms ) s ( ct Tj=150°C Tc=25°C 0.1 Single pulse 0.01 0.1 10 1 u d o VDS(V) 100 Figure 4. Output characteristics ID (A) 8 7V 6 )- 5 6V 3 2 1 r P e 0 0 5 t e l o 10 uc od 15 s b O t(s 4 VDS=15V 6 5 4 3 1 5V 20 VGS VDD=496V ID=3.8A 0 0 VDS(V) 25 AM07177v1 VGS (V) VDS 12 AM07176v1 2 Figure 6. Gate charge vs gate-source voltage s b O t e l o ID (A) VGS=10V 7 r P e Figure 5. Transfer characteristics AM07175v1 2 4 8 6 VGS(V) Figure 7. Static drain-source on-resistance AM07178v1 RDS(on) (Ω) VGS=10V 500 10 1.9 400 1.8 8 300 6 1.7 200 4 100 2 0 0 6/17 5 10 15 20 0 25 Qg(nC) 1.6 1.5 0 DocID024435 Rev 1 1 2 3 ID(A) STDLED625H Electrical characteristics Figure 8. Capacitance variations Figure 9. Output capacitance stored energy AM07179v1 C (pF) AM07180v1 Eoss (µJ) 3.0 1000 2.5 Ciss 2.0 100 1.5 Coss 1.0 10 Crss ) s ( ct 0.5 1 0.1 1 100 10 0 0 VDS(V) Figure 10. Normalized gate threshold voltage vs temperature RDS(on) (norm) (norm) 2.5 AM07182v1 2.0 O ) 0.90 s ( t c 0.80 -25 e t e l du o r P 25 75 125 so 1.5 1.0 0.5 -75 TJ(°C) Figure 12. Maximum avalanche energy vs starting Tj b O r P e bs 1.00 EAS (mJ) 120 110 100 90 80 70 60 50 40 30 20 10 0 0 u d o VDS(V) t e l o 1.10 0.70 -75 400 500 600 Figure 11. Normalized on-resistance vs temperature AM07181v1 VGS(th) 200 300 100 AM07184v1 ID=3.8 A VDD=50 V -25 25 75 125 TJ(°C) Figure 13. Normalized BVDSS vs temperature AM07183v1 BVDSS (norm) 1.10 1.05 1.00 0.95 20 40 60 80 100 120 140 TJ(°C) 0.90 -75 DocID024435 Rev 1 -25 25 75 125 TJ(°C) 7/17 Electrical characteristics STDLED625H Figure 14. Source-drain diode forward characteristics VSD (V) 1.0 AM08888v1 TJ=150°C TJ=25°C 0.9 0.8 0.7 TJ=-50°C 0.6 0.5 0.4 ) s ( ct 0.3 0.2 0.1 0 1 3 2 4 5 u d o ISD(A) r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 8/17 DocID024435 Rev 1 STDLED625H 3 Test circuits Test circuits Figure 15. Switching times test circuit for resistive load Figure 16. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF IG=CONST VDD VGS 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. VG c u d 47kΩ 1kΩ AM01468v1 e t e ol Figure 17. Test circuit for inductive load switching and diode recovery times A A G D.U.T. FAST DIODE B B S s ( t c 3.3 μF B 25 Ω D 1000 μF s b O RG S r P e 2200 μF 3.3 μF VDD ID Vi D.U.T. Pw let AM01470v1 AM01471v1 Figure 19. Unclamped inductive waveform b O AM01469v1 L VD VDD u d o G so )- L=100μH o r P Figure 18. Unclamped Inductive load test circuit A D ) s ( t 2.7kΩ PW PW D.U.T. Figure 20. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 0 DocID024435 Rev 1 10% AM01473v1 9/17 Package mechanical data 4 STDLED625H Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 10/17 DocID024435 Rev 1 STDLED625H Package mechanical data Table 9. DPAK (TO-252) mechanical data mm Dim. Min. Typ. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 ) s ( ct 6.20 D1 5.10 E 6.40 e t e ol E1 4.70 e o r P 6.60 2.28 e1 4.40 H 9.35 L 1.00 (L1) )- s b O s ( t c L2 du L4 ro R P e V2 du 4.60 10.10 1.50 2.80 0.80 0.60 1.00 0.20 0° 8° t e l o s b O DocID024435 Rev 1 11/17 Package mechanical data STDLED625H Figure 21. DPAK (TO-252) drawing ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 0068772_K 12/17 DocID024435 Rev 1 STDLED625H Package mechanical data Figure 22. DPAK footprint (a) ) s ( ct u d o r P e t e l o ) (s s b O t c u Footprint_REV_K d o r P e t e l o s b O a. All dimensions are in millimeters DocID024435 Rev 1 13/17 Packaging mechanical data 5 STDLED625H Packaging mechanical data Table 10. DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 B1 Min. D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 P1 7.9 8.1 P2 1.9 2.1 R 40 T 0.25 W 15.7 t c u ) (s 0.35 16.3 d o r P e t e l o s b O 14/17 DocID024435 Rev 1 330 ) s ( ct 13.2 u d o r P e 50 t e l o s b O Max. 18.4 22.4 Base qty. 2500 Bulk qty. 2500 STDLED625H Packaging mechanical data Figure 23. Tape for DPAK (TO-252) 10 pitches cumulative tolerance on tape +/- 0.2 mm P0 Top cover tape T P2 D E F B1 W K0 B0 For machine ref. only including draft and radii concentric around B0 A0 D1 P1 ) s ( ct User direction of feed u d o r P e let o s b O ) s ( t c u d o Bending radius User direction of feed AM08852v1 Figure 24. Reel for DPAK (TO-252) T r P e REEL DIMENSIONS 40mm min. t e l o s b O R Access hole At slot location B D C N A Full radius Tape slot in core for tape start 25 mm min. width G measured at hub AM08851v2 DocID024435 Rev 1 15/17 Revision history 6 STDLED625H Revision history Table 11. Document revision history Date Revision 22-Mar-2013 1 Changes First release. ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 16/17 DocID024435 Rev 1 STDLED625H ) s ( ct Please Read Carefully: u d o Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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