STDVE103A
Adaptive 3.4 Gbps 3:1 TMDS/HDMI signal equalizer
Features
■
Digital video signal equalizer with 3:1 HDMI
switch
■
Compatible with the high-definition multimedia
interface (HDMI) v1.3 digital interface
■
340 MHz maximum clock speed operation
supports all video formats with deep color at
maximum refresh rates
■
3.4 Gbps data rate per channel
■
Fully automatic adaptive equalizer for cable
lengths up to 25 m
■
Selectable 50 Ω input termination to VCC:
3.135 to 3.465 V
■
Low speed control lines supply to VDD:
5 V (typ)
■
ESD HBM model: > ±5 KV for TMDS I/Os
I 2C
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Integrated open-drain
data channel (DDC)
■
5.3 V tolerant DDC and HPD I/Os
■
Lock-up free operation of I2C bus
■
0 to 400 kHz clock frequency for I2C bus
■
Low capacitance TMDS channels
■
Equalizer for signal regeneration
buffer for display
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Low output skew and jitter
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TQFP64
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Description
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The STDVE103A integrates a 4-channel 3.4 Gbps
TMDS equalizer and a 3:1 switch to select one of
the three HDMI ports. The high-speed data paths
and flow-through pinout minimize the internal
device jitter and simplify the board layout. The
equalizer overcomes the jitter effects from lossy
cables. The buffer/driver on the output can drive
the TMDS output signals over long distances.
Also, STDVE103A integrates the 50 Ω
termination resistor on all the input channels to
improve performance and reduce board space.
The device can be placed in a low-power mode by
disabling the output current drivers.
The differential signal from the HDMI/DVI ports
can be routed through the STDVE103A to
guarantee good signal quality at the HDMI
receiver.
OApplications
■
Advanced TVs supporting the HDMI/DVI
standard
■
Front projectors, LCD TVs and PDPs
■
Monitors and notebooks
Designed for very low skew, jitter and low I/O
capacitance, the switch preserves the signal
integrity to pass the stringent HDMI compliance
requirements.
■
Set-top box and DVD players
Table 1.
Device summary
Order code
Operating temperature
Package
Packaging
STDVE103ABTR
-40°C to 85°C
TQFP64
Tape and reel
STDVE103ABTY
-40°C to 85°C
TQFP64
Tray
June 2009
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www.st.com
44
Contents
STDVE103A
Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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4.1
Adaptive equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2.1
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SEL operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3
HPD pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4
DDC channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5
I2C DDC line repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6
Power-down condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.7
Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.8
Timing between HPD and DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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5.1
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3
DC electrical characteristics (I2C repeater) . . . . . . . . . . . . . . . . . . . . . . . 24
5.4
Dynamic switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.5
Dynamic switching characteristics (I2C repeater) . . . . . . . . . . . . . . . . . . 28
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Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1
Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.2
Power supply requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3
Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3.1
7
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I2C lines application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Doc ID 14911 Rev 4
STDVE103A
8
Contents
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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List of tables
STDVE103A
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Gain frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SEL operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bias parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DC specifications for TMDS differential inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DC specifications for TMDS differential outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC specifications for SEL (S1, S2) inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input termination resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
External reference resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DDC I/O pins (switch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Status pins (HPD_SINK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Status pins (HPD1, HPD2, HPD3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Input/output SDA, SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Clock and data rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Equalizer gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Differential output timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Skew times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Turn-on and turn-off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DDC I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Status pins (HPD_SINK, HPD1, HPD2, HPD3, S1, S2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
I2C repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
TQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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STDVE103A
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
STDVE103A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Equalizer functional diagram (one signal pair) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DDC I2C bus repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
STDVE103A in a digital TV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin configuration (TQFP64 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
STDVE103A gain vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Test circuit for electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TMDS output driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Test circuit for HDMI receiver and driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Test circuit for turn off and turn off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Test circuit for short circuit output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Propagation delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Turn-on and turn-off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
TSK(O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
TSK(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
TSK(D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AC waveform 1 (I2C lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Test circuit for AC measurements (I2C lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
I2C bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Typical application of I2C bus system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
TQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
TQFP64 tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
TQFP64 tray drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
TQPF64 tray drawing dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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General description
1
STDVE103A
General description
The STDVE103A is a TMDS/HDMI 3:1 switch with signal equalizer. The device is a HDMI
switch featuring an integrated 4-channel 3.4 Gbps TMDS equalizer and 3:1 switch to select
one of the three HDMI ports (either external ports or internal sources).
The high-speed data paths and flow-through pinout minimize the internal device jitter and
simplify the board layout.
The equalizer provides compensation to overcome the intersymbol interference (ISI) jitter
effects from lossy cables.
The output driver buffers the TMDS output signals over long distances.
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Also, the STDVE103A integrates the 50 Ω termination resistor on all the input channels to
improve performance and reduce board space.
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The device can operate in a low-power mode by disabling the output current drivers.
The STDVE103A is ideal for advanced TV and STB applications supporting the HDMI/DVI
standard. The differential signal from the HDMI/DVI ports can be routed through the
STDVE103A to guarantee good signal quality at the HDMI receiver. Designed for very low
skew, jitter and low I/O capacitance, the switch preserves the signal integrity to pass the
stringent HDMI compliance requirements.
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The STDVE103A provides the ability to boost the incoming TMDS signal and drive it to a
level which allows efficient signal recovery at the HDMI receiver. It is especially useful for
boosting signals for longer distance transmission when the HDMI receiver is physically
distant from the HDMI input port.
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STDVE103A
2
Block diagram
Block diagram
Figure 1.
STDVE103A block diagram
HDMI input
port A
3:1
HDMI
input
select
switch
HDMI input
port B
Input stage
Output
driver/
transmitter
Equalizer
HDMI output
port Y
HDMI input
port C
2
DDC
switch
2
DDC port B
IC
repeater
2
S1,S2
HPD port A
HPD
analog
switch
HPD port B
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HPD
port Y
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CS00061A
Equalizer functional diagram (one signal pair)
Data+
Switch
(3:1)
Equalizer
Output I
driver
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S1, S2
Quantizer
50 Ω
termination
Data- selectable
Pre-Amp
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Data+
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DDC
port Y
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HPD port C
Figure 2.
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2
DDC port C
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DDC port A
Data-
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S1,S2
REXT
Current
control
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Block diagram
STDVE103A
Figure 3.
DDC I2C bus repeater
I2C Bus Repeater
A_DDC_SDA
Y_DDC_SDA
B_DDC_SDA
C_DDC_SDA
Switch
A_DDC_SCL
B_DDC_SCL
Y_DDC_SCL
C_DDC_SCL
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S1, S2
2.1
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Application diagrams
Figure 4.
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STDVE103A in a digital TV
Game
console
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DVD-R
STB
Digital TV
STDVE103A
HDMI receiver
CS00063A
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Doc ID 14911 Rev 4
STDVE103A
Pin configuration
SCL2
SDA2
HPD2
VDD
53
52
51
50
49
VCC
A21
B22
56
55
B21
A22
57
54
B23
GND
A23
61
60
59
VCC
62
A14
1
47
B14
SCL 3
2
46
VCC
GND
3
45
A13
B31
4
44
B13
A31
5
43
GND
VCC
6
B32
7
A32
8
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A12
41
B12
40
VCC
29
30
31
32
SCL_SINK
SDA_SINK
HPD_SINK
S1
S2
28
NC
33
GND
HPD 1
34
27
SDA 1
35
Z1
SCL 1
36
26
37
Y1
A11
B11
25
39
38
VCC
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Z2
16
23
REXT
Y2
15
22
GND
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GND
14
21
A34
Z3
13
20
B 34
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Y3
VCC
12
19
11
VCC
A33
18
B33
STDVE103A
Z4
9
10
42
Y4
GND
Table 2.
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SDA 3
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A24
B24
HPD3
63
Pin configuration (TQFP64 package)
64
Figure 5.
17
3
Pin configuration
Pin description
Pin number
Pin name
Type
1-2
SDA3, SCL3
I/O
3
GND
Power
4-5
B31, A31
Input, TMDS
6
VCC
Power
7-8
B32, A32
Input, TMDS
9
GND
Power
10-11
B33, A33
Input, TMDS
12
VCC
Power
13-14
B34, A34
Input, TMDS
15
GND
Power
Function
Port3 DDC bus data and clock lines
Ground
Port 3 differential inputs for channel 1
Supply voltage (3.3 V ± 5%)
Port 3 differential inputs for channel 2
Ground
Port 3 differential inputs for channel 3
Supply voltage (3.3 V ± 5%)
Port 3 differential inputs for channel 4
Ground
Doc ID 14911 Rev 4
9/44
Pin configuration
STDVE103A
Table 2.
Pin description (continued)
Pin number
Pin name
Type
Function
16
REXT
Analog
Connect to GND through a 4.7 K ± 1% precision
reference resistor. Sets the output current to
generate the output voltage compliant with TMDS
17-18
Y4, Z4
Output,
TMDS
Channel 4 differential outputs
19
VCC
Power
Supply voltage (3.3 V ± 5%)
20-21
Y3, Z3
Output,
TMDS
Channel 3 differential outputs
22
GND
Power
Ground
23-24
Y2, Z2
Output,
TMDS
Channel 2 differential outputs
25
VCC
Power
Supply voltage (3.3 V ± 5%)
26-27
Y1, Z1
Output,
TMDS
Channel 1 differential outputs
28
GND
Power
Ground
29
SCL_SINK
I/O
30
SDA_SINK
I/O
31
du
32-33
o
r
P
34
35
s
b
O
10/44
S1,S2
r
P
e
t
e
l
o
Sink side DDC bus clock line
s
b
O
Sink side DDC bus data line
Input
Input
Source select inputs
NC
No connect
HPD1
Output
36
SDA1
I/O
Port 1 DDC bus data line
37
SCL1
I/O
Port 1 DDC bus clock line
38-39
B11, A11
Input, TMDS
40
VCC
Power
41-42
B12, A12
Input, TMDS
43
GND
Power
44-45
B13, A13
Input, TMDS
46
VCC
Power
47-48
B14, A14
Input, TMDS
49
VDD
Power
Supply voltage (5.0 V ± 10%) for DDC, HPD and
source selector pins
50
HPD2
Output
Port 2 hot plug detector output
51
SDA2
I/O
ete
ol
s
(
t
c
u
d
o
Sink side hot plug detector input
High: 5 V power signal asserted from source to
sink and EDID is ready
Low: No 5 V power signal is asserted from source
to sink or EDID is not ready
)-
HPD_SINK
)
s
(
ct
Port 1 hot plug detector output.
Port 1 differential inputs for channel 1
Supply voltage (3.3 V ± 5%)
Port 1 differential inputs for channel 2
Ground
Port 1 differential inputs for channel 3
Supply voltage (3.3 V ± 5%)
Port 1 differential inputs for channel 4
Port 2 DDC bus data line
Doc ID 14911 Rev 4
STDVE103A
Pin configuration
Table 2.
Pin description (continued)
Pin number
Pin name
Type
52
SCL2
I/O
53-54
B21, A21
Input, TMDS
55
VCC
Power
56-57
B22, A22
Input, TMDS
58
GND
Power
59-60
B23, A23
61
VCC
Power
62-63
B24, A24
Input, TMDS
64
HPD3
Function
Port 2 DDC bus clock line
Port 2 differential inputs for channel 1
Supply voltage (3.3 V ± 5%)
Port 2 differential inputs for channel 2
Ground
Input, TMDS Port 2 differential inputs for channel 3
Supply voltage (3.3 V ± 5%)
)
s
(
ct
Port 2 differential inputs for channel 4
Port 3 hot plug detector output.
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Doc ID 14911 Rev 4
11/44
Functional description
4
STDVE103A
Functional description
The STDVE103A routes physical layer signals for high bandwidth digital video and is
compatible with low voltage differential signaling standards such as the TMDS. The device
passes the differential inputs from a video source to a common display when it is in the
active mode of operation. The device conforms to the TMDS standard on both inputs and
outputs.
The low on-resistance and low I/O capacitance of the switch in STDVE103A result in a very
small propagation delay. The device integrates SPDT-type switches for 3 differential data
TMDS channels and 1 differential clock channel. Additionally, it integrates the switches for
DDC and HPD line switching with I2C repeater on the DDC lines.
)
s
(
ct
The I2C interface of the selected input port is linked to the I2C interface of the output port,
and the hot plug detector (HPD) of the selected input port is output to HPD_SINK. For the
unused ports, the I2C interfaces are isolated and the HPD pins are driven to L state.
4.1
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d
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P
e
Adaptive equalizer
t
e
l
o
The equalizer dramatically reduces the intersymbol interference (ISI) jitter and attenuation
from long or lossy transmission media. The inputs present high impedance when the device
is not active or when VCC is absent or 0 V. In all other cases, the 50 Ω termination resistors
on input channels are present.
s
b
O
This circuit helps to improve the signal eye pattern significantly. Shaping is performed by the
gain stage of the equalizer to compensate the signal degradation and then the signals are
driven on to the output ports.
)
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t
c
u
The equalizer is fully adaptive and automatic in function providing smaller gain at low
frequencies and higher gain at high frequencies. The equalizer is optimized internally for an
adaptive operation.
P
e
Table 3.
let
o
s
b
O
12/44
d
o
r
Gain frequency response
Frequency
Gain in dB
(MHz)
225
3
325
5
410
6.5
825
11
1650
16
Doc ID 14911 Rev 4
STDVE103A
Functional description
Figure 6.
STDVE103A gain vs. frequency
)
s
(
ct
u
d
o
r
P
e
The STDVE103A equalizer is fully adaptive and automatic in function. The equalizer’s
performance is optimized for all frequencies over the cable lengths from 1 m to 25 m.
t
e
l
o
Input termination
s
b
O
The STDVE103A integrates precise 50 Ω ± 5% termination resistors, pulled up to VCC, on all
its differential input channels. External terminations are not required. This gives better
performance and also minimizes the PCB board space. These on-chip termination resistors
should match the differential characteristic impedance of the transmission line. Since the
output driver consists of current steering devices, an output voltage is not generated without
a termination resistor. Output voltage levels are dependent on the value of the total
termination resistance. The STDVE103A produces TMDS output levels for point-to-point
links that are doubly terminated (100 Ω at each end). With the typical 10 mA output current,
the STDVE103A produces an output voltage of 3.3 – 0.5 V = 2.8 V when driving a
termination line terminated at each end. The input terminations are selectable thus saving
power for the unselected ports.
)
(s
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Output buffers
s
b
O
Each differential output of the STDVE103A drives external 50 Ω load (pull-up resistor) and
conforms to the TMDS voltage standard. The output drivers consist of 10 mA differential
current-steering devices.
The driver outputs are short-circuit current limited and are high-impedance to ground when
S1, S2 = HL or the device is not powered. The current steering architecture requires a
resistive load to terminate the signal to complete the transmission loop from VCC to GND
through the termination resistor. Because the device switches the direction of the current
flow and not voltage levels, the output voltage swing is determined by VCC minus the voltage
drop across the termination resistor. The output current drivers are controlled by the S1, S2
pin and are turned off when S1, S2 is a HL. A stable 10 mA current is derived by accurate
internal current mirrors of a stable reference current which is generated by band-gap voltage
across the REXT. The differential output driver provides a typical 10 mA current sink
capability, which provides a typical 500 mV voltage drop across a 50 Ω termination resistor.
Doc ID 14911 Rev 4
13/44
Functional description
STDVE103A
TMDS voltage levels
The TMDS interface standard is a signaling method intended for point-to-point
communication over a tightly controlled impedance medium. The TMDS standard uses a
lower voltage swing than other common communication standards, achieving higher data
rates with reduced power consumption while reducing EMI emissions and system
susceptibility to noise. The device is capable of detecting differential signals as low as
100 mV within the entire common mode voltage range.
)
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14/44
Doc ID 14911 Rev 4
STDVE103A
Functional description
4.2
Operating modes
4.2.1
SEL operating modes
The active source is selected by configuring source select inputs, S1 and S2. The selected
TMDS inputs from each port are switched through a 3-to-1 multiplexer. The I2C interface of
the selected input port is linked to the I2C interface of the output port, and the hot plug
detector (HPD) of the selected input port is output to HPD_SINK.
Table 4.
SEL operating modes
Control pins
I/O selected
Hot-plug detect status
SCL_SINK
S1
Y/Z
H
H
A1/B1 terminations
of A2/B2 and A3/B3
are disconnected
SCL1
SDA1
HPD_SINK
L
A2/B2 terminations
of A1/B1 and A3/B3
are disconnected
SCL2
SDA2
Z
HPD_SINK
Z
L
A3/B3 terminations
of A1/B1 and A2/B2
are disconnected
SCL3
SDA3
Z
Z
HPD_SINK
H
None (Z).
All terminations are
disconnected
None (Z).
Pulled high by
external
termination
Z
Z
Z
H
L
L
HPD1
SDA_SINK
O
)
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bs
HPD2
)
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S2
Z
HPD3
Z
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H: logic high; L: logic low; X: don't care; Z: high impedance
4.3
r
P
HPD pins
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O
4.4
The input pin HPD_SINK is 5 V tolerant, allowing direct connection to 5 V signals. The
switch is able to pass both 0 V and 5 V signal levels. The HPD_SINK is an input pin while
the HPD1, HPD2 and HPD3 are outputs.
DDC channels
The DDC channels are designed with a bidirectional NMOS gate, providing 5 V signal
tolerance. The 5 V tolerance allows direct connection to a standard I2C bus, thus eliminating
the need for a level shifter. There should be external pull-up resistors on either side of the
device on both the SCL and SDA lines.
Doc ID 14911 Rev 4
15/44
Functional description
STDVE103A
I2C DDC line repeater
4.5
The device contains two identical bidirectional open-drain, non-inverting buffer circuits that
enable I2C DDC bus lines to be extended without degradation in system performance. The
STDVE103A buffers both the serial data (DDC SDA) and serial clock (DDC SCL) on the I2C
bus, while retaining all the operating modes and features of the I2C system. This enables
two buses of 400 pF bus capacitance to be connected in an I2C application. These buffers
are operational from a supply voltage of 3.0 to 3.6 V.
The I2C bus capacitance limit of 400 pF restricts the number of devices and bus length. The
STDVE103A enables the system designer to isolate the two halves of a bus,
accommodating more I2C devices or longer trace lengths. It can also be used to run two
buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the 100 kHz
bus is isolated when 400 kHz operation of the other bus is required. The STDVE103A can
be used to run the I2C bus at both 5 V and 3.3 V interface levels.
)
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ct
Two or more STDVE103As cannot be connected in series. The STDVE103A design does
not allow this configuration. Since there is no direction pin, slightly different “legal” low
voltage levels are used to avoid lock-up conditions between the input and output. A valid low
applied at the input of STDVE103A is propagated as a buffered low with a slightly higher
value on the enabled outputs.
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P
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o
When this buffered low is applied to another STDVE103A in series, the second STDVE103A
will not recognize it as a valid low and will not propagate it as a buffered low again.
s
b
O
The S1 and S2 (SEL) lines act as control signals for the corresponding A, B or C ports. Note
that the SEL line has an internal pull-down resistor. The SEL line should not change state
during an I2C operation, because disabling during bus operation hangs the bus and
enabling part way through a bus cycle could confuse the I2C parts being enabled. The SEL
input should change state only when the global bus and the repeater port are in idle state, to
prevent system failures.
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The output low levels for each internal buffer are approximately 0.5 V, but the input voltage
of each internal buffer must be 70 mV or more below the output low level, when the output
internally is driven low. This prevents a lock-up condition from occurring when the input low
condition is released.
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P
e
As with the standard I2C system, pull up resistors are required to provide the logic high
levels on the buffered bus. The STDVE103A has standard open collector configuration of
the I2C bus. The size of the pull up resistors depends on the system, but each side of the
repeater must have a pull up resistor.
t
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s
b
O
4.6
This part is designed to work with standard mode and fast mode I2C devices. Standard
mode I2C devices only specify 3 mA output drive, this limits the termination current to 3 mA
in a generic I2C system where standard mode devices and multiple masters are possible.
Under certain conditions, higher termination currents can be used.
Power-down condition
The HL combination of S1, S2 is used to disable most of the internal circuitry of
STDVE103A that puts the device in a low power mode of operation.
16/44
Doc ID 14911 Rev 4
STDVE103A
4.7
Functional description
Bias
The bandgap reference voltage over the external REXT reference resistor sets the internal
bias reference current. This current and its factors (achieved by employing highly accurate
and well matched current mirror circuit topologies) are generated on-chip and used by
several internal modules. The 10 mA current used by the transmitter block is also generated
using this reference current. It is important to ensure that the REXT value is within the ±1%
tolerance range of its typical value.
Table 5.
Bias parameter
Parameter
Bandgap voltage
Min
Typ
Max
Unit
-
1.2
-
)
s
(
ct
V
The output voltage swing depends on 3 components: supply voltage (Vsupply), termination
resistor (RT) and current drive (Idrive). The supply voltage can vary from 3.3 V ±5%,
termination resistor can vary from 50 Ω ±10%.
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d
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P
e
The voltage on the output is given by:
t
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o
V supply – I drive × R T
s
b
O
The variation on Idrive must be controlled to ensure that the voltage on HDMI output is within
the HDMI specification under all conditions.
This is achieved when:
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)
(s
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r
400mV ≤Idrive × R T ≤600mV
P
e
t
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o
with typical value centered at 500 mV.
s
b
O
4.8
Timing between HPD and DDC
It is important to ensure that the I2C DDC interface is ready by the time the HPD detection is
complete.
As soon as the discovery is finished by the HPD detection, the configuration data is
exchanged between a source and sink through the I2C DDC interface. The STDVE003’s
DDC interface is ready for communication as soon as the power supply to the chip is
present and stable. When the desired port is enabled and the chip is out of shutdown mode,
the I2C DDC lines can be used for communication.
Thus, as soon as the HPD detection sequence is complete, the DDC interface can be
readily used. There is no delay between the HPD detection and I2C DDC interface to be
ready.
Doc ID 14911 Rev 4
17/44
Maximum rating
5
STDVE103A
Maximum rating
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 6.
Absolute maximum ratings
Symbol
Parameter
Value
)
s
(
ct
VCC
Supply voltage to ground
-0.5 to +4.0
V
VDD
Supply voltage to Ground (DDC, HPD, S1, S2)
-0.5 to +6.0
V
DC input voltage (TMDS ports)
1.7 to +4.0
VI
SDA1, SCL1, SDA2, SCL2, SDA3, SCL3,SDA_SINK,
SCL_SINK, HPD_SINK, HPD1, HPD2, HPD3, S1, S2
IO
DC output current
TSTG
TL
so
Lead temperature (10 sec)
Thermal data
)
(s
b
O
Symbol
Parameter
ΘJA
Thermal coefficient (junction-ambient)
t
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P
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Doc ID 14911 Rev 4
du
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let
Storage temperature
Table 7.
18/44
Unit
V
-0.5 to +6.0
V
120
mA
-65 to +150
°C
300
°C
TQFP-64
Unit
35
°C/W
STDVE103A
Maximum rating
5.1
Recommended operating conditions
5.2
DC electrical characteristics
TA = -40 to +85 °C, VCC = 3.3 V ± 5% (a)
Table 8.
Power supply characteristics
Value
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
VCC
Supply voltage
3.135
3.3
3.465
VDD
Supply voltage
4.5
5.0
5.5
ICC
All inputs/outputs are
enabled.
Inputs are terminated
with 50 Ω to VCC.
Supply current
-
-
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ol
-
VCC = 3.465 V
-
Data rate = 3.4 Gbps
ICC
Supply current
IDD
Supply current
(VDD supply)
Table 9.
Parameter
o
s
b
CIN
300
mA
-
20
mA
2
5
mA
Value
Test condition
Unit
Min
Typ
Max
Differential input high
threshold
(peak-to-peak)
VCC = 3.465 V
over the entire VCMR
-
0
150
mV
Differential input low
threshold
VCC = 3.465 V
over the entire VCMR
-150
0
-
mV
Differential input
voltage
(peak-to-peak)(1)
VCC = 3.465 V
150
-
1560
mV
VCC - 0.04
V
-
pF
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l
VTL
VCMR
ct
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VTH
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)
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Pr
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V
DC specifications for TMDS differential inputs
Symbol
VID
S1, S2 = HL
)
s
(
ct
V
Pr
Common mode
voltage range
Input capacitance
VCC - 0.3
IN+ or IN- to GND
F = 1 MHz
-
3.5
1. Differential output voltage is defined as | (OUT+ - OUT-) |.
Differential input voltage is defined as | (IN+ - IN-) |.
a. Typical parameters are measured at VCC = 3.3 V, TA = +25 °C.
Doc ID 14911 Rev 4
19/44
Maximum rating
Table 10.
STDVE103A
DC specifications for TMDS differential outputs
Value
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
VOH
Single-ended high level
output voltage
VCC-10
-
VCC+10
mV
VOL
Single-ended low level
output voltage
VCC-600
-
VCC-400
mV
mV
Single ended output
swing voltage
VCC = 3.3 V
RTERM = 50 Ω
400
500
600
VOD
Differential output
voltage
(peak-to-peak)(1)
VCC = 3.3 V
RTERM = 50 Ω
800
1000
1200
IOL
Differential output low
level current
8
10
|ISC|
Output driver shortcircuit current
(continuous)
OUT± = GND
through a 50 Ω
resistor.
See Figure 11
-
-
Output capacitance
OUT+ or OUTto GND when tristate
F = 1 MHz
Vswing
COUT
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5.5
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du
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20/44
Doc ID 14911 Rev 4
mA
12
mA
-
pF
1. Differential output voltage is defined as | (OUT+ - OUT-) |. Differential input voltage is defined as | (IN+ - IN-) |
s
(
t
c
mV
STDVE103A
Table 11.
Maximum rating
DC specifications for SEL (S1, S2) inputs
Value
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
VIH
HIGH level input voltage
High level
guaranteed
2.0
−
−
V
VIL
LOW level input voltage
Low level
guaranteed
-0.5
−
0.8
V
VIK
Clamp diode voltage
VCC = 3.465 V
IIN = -18 mA
-1.2
-0.8
−
V
IIH
Input high current
VCC = 3.465 V
VIN = VCC
-5
−
+5
IIL
Input low current
VCC = 3.465 V
VIN = GND
-5
−
+5
CIN
Input capacitance
Pin to GND
F = 1 MHz
−
3.5
Table 12.
Input termination resistor
Symbol
RTERM
Table 13.
Parameter
Differential input
termination resistor on
IN± channels relative to
VCC
IIN = -10 mA
)
(s
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s
b
O
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Test condition
45
)
s
(
ct
−
Value
50
µA
µA
pF
Unit
55
Ω
External reference resistor
od
Symbol
Parameter
r
P
e
Resistor for TMDS
compliant voltage swing
range
let
REXT
o
s
b
Value
Test condition
Tolerance for
R = ±1%
Unit
Min
Typ
Max
−
4.7
−
KΩ
O
Doc ID 14911 Rev 4
21/44
Maximum rating
Table 14.
STDVE103A
DDC I/O pins (switch)
Value
Symbol
VI(DDC)
II(leak)
CI/O
Table 15.
Parameter
Max
GND
−
5.3
V
VCC = 3.465 V
A, B, C ports = 5.3 V
Y port = 0.0 V
Switch is isolated
−
−
6
µA
VCC = 3.465 V
A, B, C ports = 3.3 V
Y port = 0.0 V
Switch is isolated
−
−
2
VI=0 V
F = 1 MHz
Switch disabled
−
5
u
d
o
pF
9
−
pF
VI=0 V
F = 1 MHz
Switch enabled
o
s
b
Status pins (HPD_SINK)
Parameter
VIL
Low level input voltage
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)
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(
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let
−
-O
−
r
P
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Input/output capacitance
High level input voltage
s
b
O
Typ
Input leakage current
VIH
II(leak)
Unit
Min
Input voltage
Symbol
22/44
Test condition
)
s
(
ct
µA
Value
Test condition
Unit
Min
Typ
Max
VCC = 3.3 V
High level guaranteed
2.0
−
5.3
V
VCC = 3.3 V
Low level guaranteed
GND
−
0.8
V
VCC = 3.465 V
Y = 5.3 V
−
−
4
µA
VCC = 3.465 V
Y = 3.3 V
−
−
2
µA
Input leakage current
Doc ID 14911 Rev 4
STDVE103A
Table 16.
Maximum rating
Status pins (HPD1, HPD2, HPD3)(1)
Value
Symbol
V
Parameter
Test condition
Unit
Min
Typ
Max
GND
−
5.3
V
VI = 0 V
F = 1 MHz
Switch disabled
−
5
−
pF
CI/O
VI = 0 V
F = 1 MHz
Switch enabled
−
9
−
pF
VCC = 3.3 V
IOL = 8 mA
−
−
0.4
V
Voltage
Input/output capacitance
VOL
Output low voltage
(open drain I/Os)
1. Typical parameters are measured at VCC = 3.3 V, TA = +25 °C.
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Doc ID 14911 Rev 4
23/44
Maximum rating
STDVE103A
DC electrical characteristics (I2C repeater)
5.3
(TA = -40 to +85 °C, VCC = 3.3 V ± 5%, GND = 0 V; unless otherwise specified)
Table 17.
Supplies
Value
Symbol
Parameter
Test condition
VCC
DC supply voltage
Unit
Table 18.
Min
Typ
Max
3.135
3.3
3.465
V
Input/output SDA, SCL
)
s
(
t
Value
Symbol
Parameter
Test condition
Unit
Min
Typ
VIH
High level input
voltage
0.7 VCC
−
VIL
Low level input
voltage(1)
-0.5
−
VILc
Low level input voltage
contention(1)
-0.5
−
VIK
Input clamp voltage
II = -18 mA
−
IIL
Input current low
(SDA, SCL)
Input current low
(SDA, SCL)
bs
IIH
Input current high
(SDA, SCL)
VOL
IOH
let
so
b
O
CI
r
P
e
Output high level
leakage current
Input capacitance
c
u
d
5.3
V
0.3 VCC
V
0.4
V
−
-1.2
V
−
−
1
µA
VI = 3.465 V
(SDA, SCL)
−
−
10
µA
VI = 5.3 V
(SDA, SCL)
−
−
10
µA
IOL = 3 mA
0.4
V
IOL = 6 mA
0.65
V
O
)
s
(
t
c
u
d
o
LOW-level output
voltage
Max
e
t
e
ol
o
r
P
VO = 3.6 V;
driver disabled
−
−
10
µA
VO = 5.3 V;
driver disabled
−
−
10
µA
VI = 3 V or 0 V
−
6
7(2)
pF
1. VIL specification is for the first low level seen by the SDA/SCL lines. VILc is for the second and subsequent low levels seen
by the SDA/SCL lines.
2. The SCL/SDA CI is about 200 pF when VCC = 0 V. The STDVE103A should be used in applications where power is
secured to the repeater but an active bus remains on either set of the SDA/SCL pins.
24/44
Doc ID 14911 Rev 4
STDVE103A
Maximum rating
Dynamic switching characteristics(b)
5.4
TA = -40 to +85 °C, VCC = 3.3 V ± 5%, RTERM = 50 Ω ± 5%, CL = 5 pF).
Typical values are at TA = +25 °C and VCC = 3.3 V.
Table 19.
Clock and data rate
Value
Symbol
Parameter
Test condition
Clock frequency
(1/10th of the
differential data rate)
Unit
fCK
Drate
Signaling rate
Table 20.
Min
Typ
Max
25
−
340
−
−
3.4
)
s
(
ct
u
d
o
Equalizer gain
MHz
Gbps
Value
Symbol
Parameter
Test condition
Min
e
t
e
l
−
At 225 MHz
G_EQ
Equalizer gain
At 340 MHz
Table 21.
o
s
b
Differential output timings
Symbol
tr
Parameter
Differential data and
clock output rise/fall
times
Pr
Differential low to high
propagation delay
tPLH
e
t
e
l
tPHL
Differential high to low
propagation delay
Unit
Max
10
−
dB
15
−
dB
-O
Min
Typ
Max
20% to 80% of VOD
75
150
240
ps
80% to 20% of VOD
75
150
240
ps
Alternating 1 and 0 pattern
at slow and fast data rates
Measure at 50% VOD
between input to output
250
−
800
ps
250
−
800
ps
Value
Test condition
)
s
(
ct
u
d
o
tf
−
Pr
Typ
Unit
o
s
b
O
b.
The timing values in this section are tested during characterization and are guaranteed by
design and simulation. Not tested in production.
Doc ID 14911 Rev 4
25/44
Maximum rating
Table 22.
STDVE103A
Skew times
Value
Symbol
Parameter
tSK(O)
Inter-pair channel-tochannel output skew
tSK(P)
Pulse skew
tSK(D)
Intra-pair differential
skew
| tPLH - tPHL |
Output channel to
channel skew
tSK(CC)
Table 23.
Test condition
Difference in
propagation
delay
(tPLH or tPHL)
among all output
channels
Unit
Min
Typ
Max
−
−
100
ps
−
25
80
ps
−
−
50
ps
−
50
125
Value
Parameter
Min
tON
tOFF
r
P
e
let
o
s
b
Table 25.
TMDS output disable
time
Time from
OE_N to OUT±
change from
active to tristate
)
(s
ct
l
o
s
b
O
−
−
o
r
P
Unit
Typ
Max
12
20
ns
6
10
ns
DDC I/O pins
Symbol
O
Time from
OE_N to OUT±
change from tristate to active
u
d
o
Table 24.
ete
Test condition
TMDS output enable
time
ps
c
u
d
Turn-on and turn-off times
Symbol
)
s
(
t
Parameter
Value
Test condition
Unit
Min
Typ
Max
Refer to Section 5.5
Status pins (HPD_SINK, HPD1, HPD2, HPD3, S1, S2)
Value
Symbol
Parameter
Test condition
tPD(HPD)
Propagation delay
(from Y_HPD to the
active port of HPD)
TON/OFF
Switch time
(from port select to the
CL = 10 pF
latest valid status of
HPD)
26/44
CL = 10 pF,
RPU = 1 KΩ
Unit
Min
Typ
Max
−
150
−
ns
−
50
−
ns
Doc ID 14911 Rev 4
STDVE103A
Table 26.
Maximum rating
Jitter
Value
Symbol
Parameter
Test condition
PRBS pattern
at 1.6 Gbps
(800 MHz)
Total jitter(1)
tJIT
Unit
Min
Typ
Max
−
35
−
ps (p-p)
1. Total jitter is measured peak-to-peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been
subtracted. Input differential voltage = VID = 500 mV, PRBS random pattern at 1.65 Gbps, tr=tf=50 ps (20% to 80%). Jitter
parameter is not production-tested but guaranteed through characterization on a sample-to-sample basis.
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
Doc ID 14911 Rev 4
27/44
Maximum rating
STDVE103A
Dynamic switching characteristics (I2C repeater)
5.5
TA = -40 to +85 °C, VCC = 3.3 V ± 5%.
Typical values are at TA = +25 °C and VCC = 3.3 V.
Table 27.
.
I2C repeater(1)
Value
Symbol
fSCL
Parameter
Test condition
I2C clock frequency
Unit
Min
Typ
Max
Standard mode
−
−
100
kHz
Fast mode
−
−
400
kHz
−
µs
100 KHz
See Figure 19
Voltage on line = 5V
Cmax=400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20% time intervals
on both transitions.
tLOW
Low duration on SCL pin
4.7
s
b
O
−
r
P
e
t
e
l
o
400 KHz
See Figure 19
Voltage on line = 5V
Cmax = 400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20% time intervals
on both transitions.
u
d
o
)
s
(
ct
1.3
−
−
µs
100 KHz
See Figure 19
Voltage on line = 3.3 V
Cmax = 400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20% time intervals
on both transitions.
4.7
−
−
µs
s
b
O
400 KHz
See Figure 19
Voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20% time intervals
on both transitions.
1.3
−
−
µs
28/44
Doc ID 14911 Rev 4
)
(s
t
c
u
d
o
r
t
e
l
o
P
e
tLOW
Low duration on SCL pin
STDVE103A
Maximum rating
I2C repeater(1) (continued)
Table 27.
Value
Symbol
Parameter
Test condition
Unit
100 KHz
See Figure 19
Voltage on line = 5 V
Cmax = 400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20% time intervals
on both transitions
tHIGH
Min
Typ
Max
4.0
−
−
µs
High duration on SCL pin
400 KHz
See Figure 19
Voltage on line = 5 V
Cmax = 400 pF, Rmax=2 K
Depends on input signal rise time.
Includes the 20% time intervals
on both transitions
100 KHz
Refer section 14.12,
Voltage on line = 3.3 V
Cmax = 400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20% time intervals
on both transitions
0.6
−
u
d
o
)
s
(
ct
−
µs
t
e
l
o
r
P
e
4.0
−
−
µs
0.6
−
−
µs
o
s
b
Propagation delay
400 KHz
Waveform 1 (Figure 17)
Voltage on line = 5 V,
Cmax = 400 pF, Rmax = 2 K
−
−
250
µs
tPLH
Propagation delay
400 KHz
Waveform 1 (Figure 17)
Voltage on line = 5 V,
Cmax = 400 pF, Rmax = 2 K
−
−
300
µs
Propagation delay
400 KHz
Waveform 1 (Figure 17)
Voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 K
−
−
250
ns
tHIGH
)
(s
High duration on SCL pin
s
b
O
400 KHz
See Figure 19
Voltage on line = 3.3 V,
Cmax=400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20% time intervals
on both transitions
t
c
u
d
o
r
tPHL
O
tPHL
P
e
let
Doc ID 14911 Rev 4
29/44
Maximum rating
Table 27.
STDVE103A
I2C repeater(1) (continued)
Value
Symbol
tPLH
tPHL
tPLH
tPHL
tPLH
Parameter
Test condition
Typ
Max
Propagation delay
400 KHz
Waveform 1 (Figure 17)
Voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 K
−
−
450
ns
Propagation delay
100 KHz
Waveform 1 (Figure 17)
Voltage on line = 5 V,
Cmax = 400 pF, Rmax = 2 K
−
−
250
ns
Propagation delay
100 KHz
Waveform 1 (Figure 17)
Voltage on line = 5 V,
Cmax = 400 pF, Rmax = 2 K
−
Propagation delay
100 KHz
Waveform 1 (Figure 17)
Voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 K
Propagation delay
P
e
t
e
l
o
s
b
O
tf
30/44
u
d
o
r
P
e
300
ns
−
250
ns
100 KHz
Waveform 1 (Figure 17)
Voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 K
−
−
450
ns
400 KHz
Waveform 1 (Figure 17)(2)
Voltage on line = 5 V
Cmax = 400 pF, Rmax = 2 K
−
−
300
ns
400 KHz
Waveform 1(2)
Voltage on line = 3.3 V
Cmax = 400pF, Rmax = 2 K
−
−
300
ns
100 KHz
Waveform 1 (Figure 17) (2)
Voltage on line = 5 V
Cmax = 400 pF, Rmax = 2 K
−
−
300
ns
100 KHz
Waveform 1 (Figure 17)(2)
Voltage on line = 3.3 V
Cmax = 400 pF, Rmax = 2 K
−
−
300
ns
t
e
l
o
s
b
O
t
c
u
d
o
r
Output fall time
−
)
s
(
ct
−
)
(s
tf
Unit
Min
Output fall time
Doc ID 14911 Rev 4
STDVE103A
Table 27.
Maximum rating
I2C repeater(1) (continued)
Value
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
400 KHz
Waveform 1 (Figure 17)(2)
Voltage on line = 5 V
Cmax = 400 pF, Rmax = 2 K
−
−
300
ns
400 KHz
Waveform 1 (Figure 17)(2)
Voltage on line = 3.3 V
Cmax = 400 pF, Rmax = 2 K
−
−
300
ns
100 KHz
Waveform 1,(2)
Voltage on line = 5 V
Cmax = 400 pF, Rmax = 2 K
−
−
)
s
(
ct
Output rise time
tr
tr
Output rise time
100 KHz
Waveform 1 (Figure 17)(2)
Voltage on line = 3.3 V
Cmax = 400 pF, Rmax = 2 K
e
t
e
l
−
du
o
r
P
−
1000
ns
1000
ns
o
s
b
1. All the timing values are tested during characterization and are guaranteed by design and simulation. Not tested in
production.
O
)
2. The tr transition time is specified with maximum load of 2 kΩ pull-up resistance and 400 pF load capacitance. Different load
resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times.
Refer to Figure 9.
Table 28.
Symbol
du
Parameter
ro
TMDS I/Os
ESD
(HBM)
s
(
t
c
ESD performance
P
e
Other I/Os
Test conditions
Min
Typ
Max
Unit
Human body model
−
±5
−
kV
Human body model
−
±2
−
kV
t
e
l
o
s
b
O
Doc ID 14911 Rev 4
31/44
Maximum rating
Figure 7.
STDVE103A
Test circuit for electrical characteristics
VCC
CL
VOUT+
VIN+
Pulse
generator
VINRT
STDVE103A
100 Ω
VOUT-
RT
CL
)
s
(
ct
u
d
o
r
P
e
CS00065A
t
e
l
o
1. CL = load capacitance: include jig and probe capacitance.
2. RT = termination resistance; should be equal to ZOUT of the pulse generator.
Figure 8.
TMDS output driver
)
(s
t
c
u
t
e
l
o
VCC
RT
od
r
P
e
s
b
O
RT
ZO = RT
TMDS
driver
ZO = RT
TMDS
receiver
s
b
O
CS00069
1. ZO = characteristic impedance of the cable.
2. RT = termination resistance: should be equal to ZO of the cable. Both are equal to 50W.
32/44
Doc ID 14911 Rev 4
STDVE103A
Maximum rating
Figure 9.
Test circuit for HDMI receiver and driver
VCC
RT
RT
A
VA
RT
Y
VID
TMDS
receiver
CL =
0.5pF
TMDS
driver
VCC
VY
B
Z
VID = VA - VB
VB
VSwing = VY - VZ
)
s
(
ct
RT
VZ
u
d
o
r
P
e
t
e
l
o
1. RT = 50 Ω.
)
(s
CS00071
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
Doc ID 14911 Rev 4
33/44
Maximum rating
STDVE103A
Figure 10. Test circuit for turn off and turn off times
10µF
0.1 µF 0.01µF
CL
1.15 V
VCC
VIN+
1.0 V
50 Ω
)
s
(
ct
1.2 V
50 Ω
STDVE103A
1.15 V
u
d
o
VIN1.0 V
r
P
e
SHDN_N
CL
REXT
Pulse
generator
4.7 KΩ±1%
50 Ω
)
(s
s
b
O
ct
u
d
o
1. CL = 5 pF
t
e
l
o
GND
CS00072A
Figure 11. Test circuit for short circuit output current
r
P
e
t
e
l
o
bs
50 Ω
ISC
TMDS
driver
50 Ω
O
34/44
0V or 3.465 V
Doc ID 14911 Rev 4
STDVE103A
Maximum rating
Figure 12. Propagation delays
VCC
VA
VCM
VID
VCM
VB
VCC – 0.4
0.4V
VID
VID
VID(p-p)
0V
)
s
(
ct
-0.4V
u
d
o
tpHL
VOD(O)
tpLH
100%
80%
80%
VOD(p-p)
20%
ete
Output
l
o
s
tr
Pr
0V Differential
20%
0%
VOD(U)
tf
b
O
Figure 13. Turn-on and turn-off times
SHDN_N
)
(s
t
c
u
od
let
r
P
e
O
o
s
b
3.0 V
1.50 V
1.50 V
0V
tOFF
tON
VOH
VOUT+ when VID= +150mV
VOUT- when VID= -150mV
50%
50%
1.2 V
tON
tOFF
1.2 V
VOUT+ when VID= -150mV
VOUT- when VID= +150mV
50%
50%
VOL
Doc ID 14911 Rev 4
35/44
Maximum rating
STDVE103A
Figure 14. TSK(O)
3.5V
2.5V
Data In
1.5V
tpLHX
tpHLX
VOH
2.5V
2.5V
Data Out at Port 0
VOL
)
s
(
ct
tSK(o)
VOH
du
Data Out at Port 1
tpLHY
e
t
e
ol
tSK(o) = | tpLHy – tpLHx | or | tpHLy – tpHLx |
Figure 15. TSK(P)
)
(s
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
36/44
Figure 16. TSK(D)
Doc ID 14911 Rev 4
o
r
P
tpHLY
2.5V
VOL
STDVE103A
Maximum rating
Figure 17. AC waveform 1 (I2C lines)
Figure 18. Test circuit for AC measurements (I2C lines)
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
P
e
s
b
O
t
e
l
o
Figure 19. I2C bus timing
Doc ID 14911 Rev 4
37/44
Application information
STDVE103A
6
Application information
6.1
Power supply sequencing
Proper power-supply sequencing is advised for all CMOS devices. It is recommended to
always apply VCC before applying any signals to the input/output or control pins.
6.2
Power supply requirements
Bypass each of the VCC pins with 0.1 μF and 1 nF capacitors in parallel as close to the
device as possible, with the smaller-valued capacitor as close to the VCC pin of the device as
possible.
)
s
(
ct
All VCC pins can be tied to a single 3.3 V power source. A 0.01 μF capacitor is connected
from each VCC pin directly to ground to filter supply noise. The maximum power supply
variation can only be ±5% as per the HDMI specifications.
u
d
o
r
P
e
The maximum tolerable noise ripple on 3.3 V supply must be within a specified limit.
6.3
t
e
l
o
Differential traces
s
b
O
The high-speed TMDS inputs are the most critical parts for the device. There are several
considerations to minimize discontinuities on these transmission lines between the
connectors and the device.
)
(s
(a) Maintain 100-Ω differential transmission line impedance into and out of the STDVE103A.
t
c
u
(b) Keep an uninterrupted ground plane below the high-speed I/Os.
(c) Keep the ground-path vias to the device as close as possible to allow the shortest return
current path.
d
o
r
(d) Layout of the TMDS differential inputs should be with the shortest stubs from the
connectors.
P
e
t
e
l
o
s
b
O
38/44
Output trace characteristics affect the performance of the STDVE103A. Use controlled
impedance traces to match trace impedance to both the transmission medium impedance
and termination resistor. Run the differential traces close together to minimize the effects of
the noise. Reduce skew by matching the electrical length of the traces. Avoid discontinuities
in the differential trace layout. Avoid 90 degree turns and minimize the number of vias to
further prevent impedance discontinuities.
Doc ID 14911 Rev 4
STDVE103A
Application information
I2C lines application information
6.3.1
A typical application is shown in the figure below. In the example, the system master is
running on a 3.3 V I2C-bus while the slave is connected to a 5 V bus. Both buses run at
100 kHz unless the slave bus is isolated and then the master bus can run at 400 kHz.
Master devices can be placed on either bus.
Figure 20. Typical application of I2C bus system
3.3V
5.0V
SDA
SDA
SCL
SCL
SCL
STDVE103A
SEL
Bus Master
400 kHz
O
)
SDA
e
t
e
ol
bs
BUS 0
u
d
o
SDA
SHDN_N
)
s
(
ct
Pr
SCL
Slave
100 kHz
BUS 1
AM00712V1
The STDVE103A DDC lines are 5 V tolerant; so it does not require any extra circuitry to
translate between the different bus voltages.
s
(
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
Doc ID 14911 Rev 4
39/44
Package mechanical data
7
STDVE103A
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 21. TQFP64 package outline
A
D
A2
D1
)
s
(
ct
A1
D3
33
48
u
d
o
0.10mm
32
49
.004
1
)16
e
s
(
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
40/44
Doc ID 14911 Rev 4
L
17
r
P
e
t
e
l
o
s
b
O
L1
64
E
E1
E3
B
Seating Plane
K
C
0051434/E
STDVE103A
Package mechanical data
Table 29.
TQFP64 mechanical data
Millimeters
Symbol
Min
Typ
Max
A
−
−
1.20
A1
0.05
0.10
0.15
A2
0.95
1
1.05
b
0.17
0.22
0.27
c
0.09
0.15
0.20
D
11.80
12
12.20
D1
9.80
10
D3
−
7.50
E
11.80
12
E1
9.80
10
E3
−
7.50
e
−
L
0.45
L1
−
K
0°
e
t
e
l
0.50
o
s
b
O
)
)
s
(
ct
10.20
o
r
P
du
−
12.20
10.20
−
−
0.60
0.75
1
−
−
7°
Figure 22. TQFP64 tape and reel information
s
(
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
Doc ID 14911 Rev 4
41/44
Package mechanical data
STDVE103A
Figure 23. TQFP64 tray drawing
)
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Figure 24. TQPF64 tray drawing dimensions
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Revision history
Revision history
Table 30.
Document revision history
Date
Revision
21-Jul-2008
1
Initial release.
2
Changed Table 1: Device summary on page 1 to add new order
code.
Modified the hot-plug detect status in Table 4: SEL operating modes
on page 15.
Updated ESD information in the Features section and Table 28: ESD
performance on page 31
Added TQFP64 tray drawing in Figure 23: TQFP64 tray drawing on
page 42 and Figure 24: TQPF64 tray drawing dimensions on
page 42.
09-Sept-2008
Changes
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27-Mar-2009
3
Updated: Features section and thermal junction value in Chapter 5:
Maximum rating.
01-Jun-2009
4
Updated: Table 10.
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STDVE103A
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